FERROELECTRIC MEMORY DEVICE

• US 3,832,700 A
• Filed: 04/24/1973
• Issued: 08/27/1974
• Est. Priority Date: 04/24/1973
• Status: Expired due to Term

• Current Assignee: Maurice Hubert Francombe, Shu-Yau Wu
• Original Assignee: Maurice Hubert Francombe, Shu-Yau Wu
• Inventors: Wu, Shu-Yau, Francombe, Maurice Hubert
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/354,022
• Time in Patent Office: 490 Days
• Field of Search: 340/173R,173.2 317/235B 307/304
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A ferroelectric memory device utilizing the remanent polarization of a thin, ferroelectric film to control the surface conductivity of a bulk semiconductor and perform the memory function. The structure of the device is similar to a conventional MIS field effect transistor with the exception that the gate insulating layer is replaced by a thin film of active ferroelectric material comprising a reversably polarizable dielectric exhibiting hysteresis.

Claims

2. The memory device of claim 1 wherein said film is formed by sputtering techniques.

3. The memory device of claim 1, with no injection and extraction of carriers at the ferroelectric-semiconductor interface, wherein said substrate is formed from P-type semiconductive material, said spaced regions are N+-type, and wherein an inversion layer defining an N-type channel connecting said N+-type regions is formed when a potential is applied and then removed between said ferroelectric film and said substrate such that the film is positive with respect to the substrate.

4. The memory device of claim 1, with no injection and extraction of carriers at the ferroelectric-semiconductor interface, wherein said substrate is formed from N-type semiconductive material and said spaced regions are P+-type, and wherein an inversion layer forming a P-type channel between said P+-type regions is formed when a potential is applied and then removed between said ferroelectric film and said substrate such that the film is negative with respect to the substrate.

5. The memory device of claim 1, with injection and extraction of carriers at the ferroelectric-semiconductor interface, wherein said substrate is formed from P-type semiconductive material, said spaced regions and N+-type, and wherein an inversion layer defining an N-channel connecting said N+-type regions is formed when a potential is applied and then removed between said ferroelectric film and said substrate such that the film is negative with respect to the substrate.

6. The memory device of claim 1, with injection and extraction of carriers at the ferroelectric-semiconductor interface, wherein said substrate is formed from N-type semiconductive material and said spaced regions are P+-type, and wherein an inversion layer forming a P-type channel between said P+-type regions is formed when a potential is applied and then removed between said ferroelectric film and said substrate such that the film is positive with respect to the substrate.

7. The memory device of claim 1 including metallizations in contact with said spaced regions and a metallization overlying said film of ferroelectric material spanning the space between said regions, the metallization over said ferroelectric film acting as a gate electrode and the metallization in contact with said spaced regions forming the source and drain electrodes of a field effect transistor structure.

8. The memory device of claim 1 wherein said ferroelectric material comprises bismuth titanate.