A-C VOLTAGE DETECTOR

• US 3,836,790 A
• Filed: 08/22/1973
• Issued: 09/17/1974
• Est. Priority Date: 08/22/1973
• Status: Expired due to Term

• Current Assignee: Dustin J. Becker
• Original Assignee: Dustin J. Becker
• Inventors: Becker, Dustin J.
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/390,349
• Time in Patent Office: 391 Days
• Field of Search: 307/235,295 317/31,27R,DIG.5 340/248R,248A,248C
• US Class Current: 327/74
• CPC Class Codes: H02H 3/207 also responsive to under-voltage window comparators for indication G01R19/165
• CPC Class Codes: H02H 3/253 for multiphase applications, e.g. phase interruption

Abstract

A circuit for detecting whether the peak magnitude of one or more phases of a polyphase voltage has varied outside of acceptable high and low voltage limits. A high voltage detecting network produces a first voltage when the peak amplitude of the input voltage remains below an acceptable maximum and produces a second voltage when the peak amplitude of the input voltage exceeds that acceptable maximum. A low voltage detecting network produces a first voltage when the peak amplitude of the input voltage exceeds an acceptable minimum and produces a second voltage when the peak amplitude of the input voltage fails to exceed that acceptable minimum. A timing network indicates a fault condition if either detector produces its second voltage on a recurrent basis for more than a predetermined time. Together these networks assure that fault indications do not occur in the presence of occasional excessive input voltage excursions or in the presence of normally occurring a-c voltage transients and thus prevent false indications of input voltage faults.

Claims

1. In a circuit for indicating whether the magnitude of an a-c voltage is within acceptable voltage limits, in combination, circuit input means, circuit output means, rectifying means for establishing a pulsating d-c voltage that varies in accordance with an a-c voltage at said circuit input means, voltage limit comparing means having input means and output means, said voltage limit comparing means serving as means for establishing a first voltage at the output means thereof when the peak amplitude of each pulsation of said pulsating d-c voltage is between a predetermined high limit reference voltage and a predetermined low limit reference voltage and for establishing a second voltage at the output means thereof each time that the peak amplitude of any pulsation of said pulsating d-c voltage does not fall between said predetermined high limit reference voltage and said predetermined low limit reference voltage, timing means having an input and an output, said timing means serving as means for establishing at said circuit output means a voltage indicative of an unacceptable input voltage condition when said voltage limit comparing means applies said second voltage to the input of said timing means on at least a periodic basis for more than a predetermined time and for establishing a voltage indicative of an acceptable input voltage condition when said voltage limit comparing means does not apply said second voltage to the input of said timing means on a periodic basis for said predetermined time.

2. A circuit as set forth in claim 1 wherein the peak value of said pulsating d-c voltage becomes equal to said predetermined high limit reference voltage when the peak value of the a-c voltage at said circuit input means attains its maximum acceptable value and wherein the peak value of said pulsating d-c voltage becomes equal to said low limit reference voltage when the peak amplitude of the a-c voltage at said circuit input means attains its lowest acceptable value.

3. A circuit as set forth in claim 1 wherein said predetermined time exceeds the duration of normally occurring transient fluctuations in the peak amplitude of the a-c voltage at said circuit input means.

4. A circuit as set forth in claim 1 wherein said circuit input means comprises polyphase a-c input means adapted to be energized by a polyphase voltage.

5. A circuit as set forth in claim 4 in which said voltage limit comparing means applies said second voltage to the input of said timing means on a periodic basis when the time between the times at which said voltage limit comparing means applies said second voltage to the input of said timing means is not substantially longer than one complete cycle of the polyphase input voltage.

6. A circuit as set forth in claim 1 wherein said timing means includes a first two-state timing network having an input and an output, said first timing network being adapted to establish one voltage at the output thereof when said second voltage is applied to the input thereof on a periodic basis and for establishing another voltage at the output thereof when said second voltage is not applied to the input thereof on a periodic basis, a second two-state timing network having an input and an output, said second timing network being adapted to establish at the output thereof said voltage indicative of an acceptable input voltage condition when said first timing network applies said another voltage to the input thereof and for establishing at the output thereof said voltage indicative of an unacceptable input voltage condition when said first timing network applies said one voltage to the input thereof for said predetermined time, means for connecting the input of said first timing network to the input of said timing means, and means for connecting the output of said second timing network to the output of said timing means.

7. A circuit as set forth in claim 6 wherein said first and second two-state timing networks each comprise retriggerable monostable multivibrators.

8. A circuit as set forth in claim 6 wherein said first and second two-state timing networks each include a Schmitt trigger having an input and an output, a resistor-capacitor network and means for connecting said resistor-capacitor network across a source of voltage and to the input of the respective Schmitt trigger.

9. A circuit as set forth in claim 1 wherein said voltage limit comparing means includes first two-state switching means for comparing said pulsating d-c voltage to said predetermined high limit reference voltage and second two-state switching means for comparing said pulsating d-c voltage to said predetermined low limit reference voltage.

10. In a circuit for indicating whether the magnitude of an a-c voltage is within acceptable voltage limits, in combination, circuit input means, circuit output means, rectifying means for establishing a pulsating d-c voltage that varies in accordance with an a-c voltage at said circuit input means, high voltage fault detecting means having an input and an output, said high voltage fault detecting means serving as means for establishing a first voltage at the output thereof when said pulsating d-c voltage remains less than a predetermined high limit reference voltage during each pulsation of said pulsating d-c voltage and for establishing a second voltage at the output thereof when said pulsating d-c voltage exceeds said predetermined high limit reference voltage, low voltage fault detecting means having an input and an output, said low voltage fault detecting means serving as means for establishing a first voltage at the output thereof when said pulsating d-c voltage varies from below to above a predetermined low limit reference voltage during each pulsation of said pulsating d-c voltage and for establishing a second voltage at the output thereof each time that said pulsating d-c voltage remains less than said predetermined low limit reference voltage during a complete pulsation of said pulsating d-c voltage, timing means having an input and an output, said timing means serving as means for establishing a voltage indicative of an unacceptable input voltage condition when either said high voltage fault detecting meAns or said low voltage fault detecting means applies said second voltage to the input of said timing means on a periodic basis for more than a predetermined time and for establishing a voltage indicative of an acceptable input voltage condition when neither said high voltage fault detecting circuitry nor said low voltage fault detecting circuitry applies said second voltage to the input of said timing means on a periodic basis for said predetermined time.

11. A circuit as set forth in claim 10 wherein said timing means includes a first two-state timing network having an input and an output, said first timing network being adapted to establish one voltage at the output thereof when said second voltage is applied to the input thereof on a periodic basis and for establishing another voltage at the output thereof when said second voltage is not applied to the input thereof on a periodic basis, a second two-state timing network having an input and an output, said second timing network being adapted to establish at the output thereof said voltage indicative of an acceptable input voltage condition when said first timing network applies said another voltage to the input thereof and for establishing at the output thereof said voltage indicative of an unacceptable input voltage condition when said first timing network applies said one voltage to the input thereof for a predetermined time, means for connecting the input of said first timing network to the input of said timing means, and means for connecting the output of said second timing network to the output of said timing means.

12. A circuit as set forth in claim 11 wherein said first and second two-state timing networks each comprise retriggerable monostable multivibrators.

13. A circuit as set forth in claim 11 wherein said first and second two-state timing networks each include a Schmitt trigger having an input and an output, a resistor-capacitor network and means for connecting said resistor-capacitor network across a source of voltage and to the input of the respective Schmitt trigger.

14. In a circuit for detecting whether an a-c voltage has a magnitude which falls within acceptable limits, in combination, circuit input means, circuit output means, rectifying means for establishing a pulsating d-c voltage that varies in accordance with an a-c voltage at said circuit input means, high voltage comparing means having an input and an output, said high voltage comparing means serving as means for establishing at the output thereof a first voltage when said pulsating d-c voltage is less than a preset high limit reference voltage and for establishing a second voltage at the output thereof when said pulsating d-c voltage exceeds said preset high limit reference voltage, low voltage comparing means having an input and an output, said low voltage comparing means serving as means for establishing a first voltage at the output thereof when said pulsating d-c voltage is less than a predetermined low limit reference voltage and for establishing a second voltage at the output thereof when said pulsating d-c voltage exceeds said preset low limit reference voltage, translating means having an input and an output, said translating means serving as means for establishing a first voltage at the output thereof when said low voltage comparing means establishes said second voltage during each pulsation of said pulsating d-c voltage and for establishing a second voltage at the output thereof for a limited time each time that said low voltage comparing means fails to establish said second voltage during each pulsation of said pulsating d-c voltage, timing means having an input and an output, said timing means serving as means for establishing at said circuit output means a voltage which indicates an unacceptable input voltage condition when said second voltage is applied to the input of said timing means on a periodic basis for more than a predetermined time and for establishing at said circuit output means a voltage which indicates an acCeptable input voltage condition when said second voltage is not applied to the input of said timing means on a non-periodic basis for more than said predetermined time, and means for connecting the output of said high voltage comparing means and the output of said translating means to the input of said timing means.

15. A circuit as set forth in claim 14 wherein said timing means includes a first two-state timing network having an input and an output, said first timing network being adapted to establish one voltage at the output thereof when said second voltage is applied to the input thereof on a periodic basis and for establishing another voltage at the output thereof when said second voltage is not applied to the input thereof on a periodic basis, a second two-state timing network having an input and an output, said second timing network being adapted to establish at the output thereof said voltage indicative of an acceptable input voltage condition when said first timing network applies said another voltage to the input thereof and for establishing at the output thereof said voltage indicative of an unacceptable input voltage condition when said first timing network applies said one voltage to the input thereof for a predetermined time, means for connecting the input of said first timing network to the input of said timing means, and means for connecting the output of said second timing network to the output of said timing means.

16. In a circuit for indicating whether the magnitude of an a-c voltage is within acceptable voltage limits, in combination, circuit input means, circuit output means, a first operational amplifier having a signal input, a reference input and an output, means for applying a high limit reference voltage to the reference input of said first operational amplifier, a second operational amplifier having a signal input, a reference input and an output, means for applying a low limit reference voltage to the reference input of said second operational amplifier, rectifying means for connecting said circuit input means to the signal inputs of said first and second operational amplifiers, a first retriggerable monostable multivibrator having a trigger input and an output, said first multivibrator being adapted to establish a first preset voltage at the output thereof for a first predetermined time each time that a trigger voltage is applied to the trigger input thereof, a second retriggerable monostable multivibrator having a trigger input and an output, said second multivibrator being adapted to establish a second preset voltage at the output thereof for a second predetermined time each time that a trigger voltage is applied to the trigger input thereof, means for connecting the output of said first operational amplifier to the trigger input of said first multivibrator, means for connecting the output of said first multivibrator to the trigger input of said second multivibrator, a third retriggerable monostable multivibrator having a trigger input and an output, said third multivibrator being adapted to establish a third preset voltage at the output thereof each time that a trigger voltage is applied to the trigger input thereof, means for connecting the output of said second operational amplifier to the trigger input of said third multivibrator, means for connecting the output of said third multivibrator to the trigger input of said first multivibrator, and means for connecting the output of said second multivibrator to said second output means.

17. In a circuit for indicating whether the magnitude of an a-c voltage is within acceptable voltage limits, in combination, circuit input means, circuit output means, a first operational amplifier having a signal input, a reference input and an output, means for applying a high limit reference voltage to the reference input of said first operational amplifier, a second operational amplifier having a signal input, reference input and an output, means for applying a low limit reference voltage to the reference input of said second operational amplifier, rectifying means for connecting said circuit input means to the signal inputs of said first and second operational amplifiers, a first two-state switching network having an input and an output, said first switching network serving as means for establishing one of two voltages at the output thereof in accordance with whether the voltage at the input thereof is above or below a first preset input voltage threshold, a first resistor-capacitor network, means for connecting said first resistor-capacitor network across a source of voltage, to the output of said first operational amplifier and to the input of said first switching network, a second two-state switching network having an input and an output, said second switching network serving as means for establishing one of two voltages at the output thereof in accordance with whether the voltage at the input thereof is above or below a second preset input voltage threshold, a second resistor-capacitor network, means for connecting said second resistor-capacitor network across a source of voltage, to the output of said first switching network and to the input of said second switching network, a third two-state switching network having a signal input and an output, said third switching network being adapted to establish one of two voltages at the output thereof in accordance with whether the voltage at the input thereof is above or below a third preset input voltage threshold, a third resistor-capacitor network, means for connecting said third resistor-capacitor network across a source of voltage and to the input of said third switching network, a discharging element for discharging said third resistor-capacitor network, means for connecting the output of said second operational amplifier in energizing relationship to said discharging element, means for connecting the output of said third switching network to the input of said first switching network, and means for connecting the output of said second switching network to said circuit output means.