CIRCUIT ARRANGEMENT FOR GENERATING PSEUDO RANDOM NUMBERS

• US 3,838,259 A
• Filed: 04/05/1973
• Issued: 09/24/1974
• Est. Priority Date: 04/07/1972
• Status: Expired due to Term

• Current Assignee: Dieter Kortenhaus
• Original Assignee: Dieter Kortenhaus
• Inventors: Kortenhaus, Dieter
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Malzahn, David H.
• Application Number:
  US05/348,221
• Time in Patent Office: 537 Days
• Field of Search: 235/152 331/78 273/138A
• US Class Current: 708/250
• CPC Class Codes: G06F 7/586 using an integer algorithm, e.g. using linear congruential method

Abstract

A circuit for generating pseudo random numbers includes an adder stage having a multiplier connected for serial bit multiple addition. The adder stage is controlled by a sequence switch. The adder stage includes a first register connected to receive a preceding random number, a second register having a constant number, means connected for the serial addition of the outputs of the first and second registers, and a sum register connected to receive the results of the multiple addition. The output of the sum register is connected to the input of the first register under control of the sequence switch. An additional register may be provided, in addition to serial subtractor means for combining the outputs of the sum register and the additional register.

Claims

1. A circuit for generating pseudo random numbers, comprising sequence switching means, first, second and third registers, adder means, means for inserting a constant number in said second register, means for applying the outputs of said first and second registers to said adder means, means applying the output of said adder means to said third register, first means responsive to said sequence switch for applying the output of said third register to said first register, second means responsive to said sequence switch for controlling circulation of data in said first register, and means for starting said sequence switch.

2. The circuit of claim 1, further comprising terminal means for connection to a source of a.c. power, means for producing a randomly occurring signal responsive to the phase position of a.c. power at said terminals, and means responsive to said sequence switching means for applying said randomly occurring signal to said first register.

3. The circuit of claim 1 in which said first, second and third registers are clock frequency operated shift registers, and further comprising a trigger circuit having an a.c. power supply input unsynchronized with the clock operation of said registers, and means responsive to said switching means for applying the output of said trigger circuit to said first register for applying a random signal thereto.

4. The circuit of claim 1, further comprising a fourth register, means applying a constant number to said fourth register, full subtractor means, and means for applying the outputs of said third and fourth registers to said full subtractor means for producing a pseudo random number.

5. The circuit of claim 4, wherein said means for applying a constant number to said fourth register comprises a source of a fixed number, and means responsive to said sequence switching means for applying the output of said source of a fixed number to said fourth register, and wherein said circuit further comprises means for circulating data in said fourth register.

6. The circuit of claim 5, wherein said fourth register is a clock operated shift register, and said subtractor means is a serial full subtractor and wherein said means applying the outputs of said third and fourth registers to said full subtractor means comprises data means responsive to said sequence switching means for applying the outputs of said third and fourth registers to said serial full subtractor means.

7. The circuit of claim 6, further comprising means responsive to the output of said serial full subtractor for controlling said sequence switching means.

8. The circuit of claim 1, wherein said means for inserting a constant number in said second register comprises a source of a fixed number, and means responsive to said switching means for applying the output of said source of a fixed number to said second register, and further comprising means for circulating data in said second register.

9. The circuit of claim 1, wherein said adder means is a serial full adder.

10. The circuit of claim 1, wherein said first, second and third registers are clock operated shift registers.

11. The circuit of claim 10, wherein said adder means is a serial full adder, said means applying the outputs of said first and second registers to said adder means comprises AND-gate means connected to apply the outputs of said first and second registers to said serial full adder as one input thereof, and further comprising means applying the output of said third register to said serial full adder as the second input thereof.