METHOD FOR POSITIONING AND BONDING

• US 3,840,978 A
• Filed: 10/12/1971
• Issued: 10/15/1974
• Est. Priority Date: 11/12/1969
• Status: Expired due to Term

• Current Assignee: Herbert Wenskus, John R. Lynch, Leonard E. Otten
• Original Assignee: Herbert Wenskus, John R. Lynch, Leonard E. Otten
• Inventors: Lynch, John R., Otten, Leonard E., Wenskus, Herbert
• Primary Examiner(s): Overholser, J. Spencer
• Assistant Examiner(s): Shore, Ronald J.
• Application Number:
  US05/188,045
• Time in Patent Office: 1,099 Days
• Field of Search: 29/493,589,471.1 228/4,5,6,44,47,49
• US Class Current: 228/110.1
• CPC Class Codes: H01L 21/67144 Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10T 29/49133 with component orienting

Abstract

This patent discloses a method and apparatus for aligning and joining a semiconductor chip to a substrate or carrier. The apparatus for first aligning and then bonding the chip to a substrate comprises a first system which includes first alignment means, immediately below the alignment means there being a substrate receiving means which is movable so as to permit alignment of the substrate in a predetermined position relative to the first alignment means. A second system cooperates with the first system and includes a vacuum-operated chip receiver. The first system is then moved until the chip is superimposed of the substrate and means are provided to press the chip into contact with the substrate. A heater located in the substrate receiving means heats the substrate and while the chip is being held against the substrate the substrate receiving means is rotated arcuately, the substrate bearing against the chip and causing a scrubbing action to inhibit the presence of voids in the bond interface.

Claims

1. A method of aligning and joining a semiconductor chip to a bondable substrate, said method comprising the steps of:

fixing one of a chip and substrate in a first system;

fixing the other of said chip and substrate in a second system, aligning one of said systems to the other of said systems until one of said chip and said substrate is aligned with the other in superimposed relation;

bringing said chip and substrate into intimate contact;

heating at least one of said chip and said substrate to a temperature sufficient to thermally bond, one to the other; and

oscillating said chip and said substrate against one another in an arcuate path to thereby inhibit the presence of voids intermediate said chip and substrate.

2. A method of aligning and joining a semiconductor chip to a bondable substrate, in accordance with claim 1, including, prior to said fixing steps, the step of separating said first system from said second-system.

3. A method of aligning and joining a semiconductor chip to a bondable substrate, in accordance with claim 1, wherein said first fixing step includes the step of aligning one of said substrate and chip to a first reference;

and then aligning said other of said chip and substrate to a second reference related to said first reference.

4. A method of aligning and joining a semiconductor chip to a bondable substrate, in accordance with claim 3, wherein said aligning of said other of said chip and substrate to a second reference includes the step of moving only said one of said chip and substrate until said second reference indicates alignment of said chip and said substrate.