METHODS OF FORMING SELF ALIGNED TRANSISTOR STRUCTURE HAVING POLYCRYSTALLINE CONTACTS

• US 3,847,687 A
• Filed: 11/15/1972
• Issued: 11/12/1974
• Est. Priority Date: 11/15/1972
• Status: Expired due to Term

• Current Assignee: Administrator Ajamie, Deceased Davidsohn
• Original Assignee: Administrator Ajamie, Deceased Davidsohn
• Inventors: Ajamie, administrator, Davidsohn, deceased
• Primary Examiner(s): Ozaki, G. T.
• Application Number:
  US05/306,762
• Time in Patent Office: 727 Days
• Field of Search: 148/187,175 317/235AT
• US Class Current: 438/353
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 21/8222 Bipolar technology
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 148/106 Masks, special
• CPC Class Codes: Y10S 148/115 Orientation
• CPC Class Codes: Y10S 148/122 Polycrystalline

Abstract

Disclosed are three processes, which all employ a common sequence of steps, for forming discrete and integrtated circuit transistors having emitters self-aligned between base enhancements and various polycrystalline silicon contacting members. The first process forms transistors having polycrystalline emitter contacts. The second process employs anisotropic etching techniques for forming self-aligned, integrated circuit transistors having polycrystalline emitter and collector contacts along with shallow isolation and collector buried layer contacting diffusions. The third process provides a transistor having polycrystalline silicon contacts to the emitter and base enhancement regions and utilizes boron doped polycrystalline silicon base contacts as an etch stop.

Claims

1. A PROCESS FOR FORMING A SILICON SEMICONDUCTOR DEVICE HAVING A FIRST REGION OF ONE CONDUCTIVITY TYPE, A CLOSELY SPACED SECOND REGION OF ANOTHER CONDUCTIVITY TYPE AND A CONTACT TO THE SECOND REGION, WHICH ARE ALL SELF-ALIGNED WITH EACH OTHER, TO FACILITATE THE MANUFACTURE OF AN ELECTRICAL DEVICE HAVING A SMALL GEOMETRY IN SEMICONDUCTOR MATERIAL WITH A SURFACE, THE PROCESS COMPRISING:

FORMING A FIRST MASK ON THE SURFACE OF THE SEMICONDUCTOR MATERIAL, SAID FIRST MASK HAVING AT LEAST A FIRST OPENING WHICH EXPOSES A SELECTED AREA OF THE SURFACE OF THE SEMICONDUCTOR MATERIAL THROUGH WHICH DIFFUSANT FORMING THE FIRST REGION IS TO ENTER AND A SECOND OPENING THROUGH WHICH DIFFUSANT FORMING THE SECOND REGION IS TO ENTER;

SAID STEP OF FORMING SAID FIRST MASK INCLUDES THE STEPS OF FORMING A FIRST SILICON DIOXIDE LAYER AND A FIRST SILICON NITRIDE LAYER, ONE ON TOP OF THE OTHER;

FORMING POLYCRYSTALLINE SILICON CONTACTING MATERIAL IN AT LEAST SAID SECOND OPENING AND ON SAID FIRST MASK, FORMING A SECOND MASK OVERLYING SAID CONTACTING MATERIAL IN SAID SECOND OPENING;

DIFFUSING FIRST DIFFUSANT THROUGH SAID FIRST OPENIG OF SAID FIRST MASK TO FORM THE FIRST REGION OF THE ONE CONDUCTIVITY TYPE, SAID SECOND MASK PREVENTING SAID FIRST DIFFUSANT FROM ENTERING SAID SEMICONDUCTOR MATERIAL THROUGH SAID SECOND OPENING;

AND CLOSING SAID FIRST OPENING IN SAID FIRST MASK AND REMOVING SAID SECOND MASK FROM SAID SECOND OPENING AND DIFFUSING SECOND DIFFUSANT THROUGH SAID CONTACTING MATERIAL AND SAID SECOND OPENING AND INTO SAID SEMICONDUCTOR MATERIAL TO FORM SAID SECOND REGION OF THE OTHER CONDUCTIVITY TYPE AND THE CONTACT THEREFOR, SAID FIRST MASK PREVENTING THE SECOND DIFFUSANT FROM OTHERWISE ENTERING THE SEMICONDUCTOR MATERIAL.

2. The process of claim 1 wherein said step of forming the contacting material in said second opening includes depositing a layer of polycrystalline silicon over said first mask and in said first and second openings in said first mask.

3. A process for forming a silicon semiconductor transistor device having an emitter contact, base enhancement regions and an emitter region which are all aligned with each other to provide a transistor in a semiconductor material having a base with a first surface and a collector formed therein, the process comprising:

forming a first mask on the first surface of the base, said first mask having openings which expose selected areas of the first surface of the base through which enhancement and emitter forming diffusions are to enter, said step of forming a first mask on the first surface of the base including;

applying a first layer of silicon dioxide on the first surface of the base;

forming a first layer of silicon nitride on said first layer of silicon dioxide;

forming a second layer of silicon dioxide on said first layer of silicon nitride;

patterning said second layer of silicon dioxide including the removal of portions of said second layer of silicon dioxide to form an etch mask for said first layer of silicon nitride;

etching said first layer of silicon nitride to form an etch layer for said first layer of silicon dioxide; and

etching said first layer of silicon dioxide;

forming a polycrystalline silicon emitter contact in said emitter opening provided in said first mask;

forming a second mask only on the emitter contact;

diffusing the enhancement regions through said first surfaces of said base exposed by said enhancement openings, said first mask and said second mask preventing the enhancement diffusants from otherwise entering the semiconductor material;

closing said enhancement openings in said first mask by forming diffusant resistant material therein;

removing said second mask from over said emitter contact; and

diffusing said emitter through the emitter contact and into said base, said first mask and said diffusant resistant material formed in said enhancement openings preventing said emitter diffusant from otherwise entering the semiconductor material.

4. The process of claim 3 wherein said step of forming the emitter contact in said emitter opening provided in said first mask includes:

forming a layer of polycrystalline silicon in said openings of said first mask and on said first mask;

providing a second layer of silicon nitride on said polycrystalline silicon layer;

providing a third layer of silicon dioxide on said second layer of silicon nitride;

etching said third layer of silicon dioxide to form an etch mask for said second layer of silicon nitride, said first layer of silicon nitride protecting said first layer of silicon dioxide during said etch of said third layer of silicon dioxide and said second layer of silicon nitride forming an etch stop;

etching said second layer of silicon nitride to complete a mask for said polycrystalline silicon layer; and

etching said polycrystalline silicon layer to form said emitter contact.

5. The process of claim 3 wherein said step of closing said enhancement openings in said first mask by forming diffusant resistant material therein includes providing a layer of silicon dioxide in said enhancement openings.

6. A process for forming a silicon semiconductor transistor device having self-aligned base enhancement and emitter regions, isolation junctions, and collector and emitter contacts for semiconductor material having a first surface, a predetermined crystallographic orientation, a collector and a buried layer, the process comprising:

forming a first mask on the first surface of the semiconductor material, said first mask having first openings which expose selected areas of the semiconductor material in which the collector contact and isolation junctions are to be provided;

anisotropically etching said exposed selected areas of the semiconductor material to remove some of the semiconductor material to provide collector and isolation grooves having sidewalls forming a predetermined included angle with the first surface of the semiconductor material, the etch rate of said anisotropic etch being substantially reduced when said sidewalls reach each other to form a point at a predetermined depth in the semiconductor material, said depth being controlled by said first mask openings;

simultaneously etching second openings through said first mask which expose areas of the semiconductor material through which self-aligned base enhancement and emitter diffusions can be performed;

providing the collector and emitter contacts respectively in said collector contact grooves and said emitter opening;

forming a second mask on said collector and emitter contacts;

simultaneously diffusing the enhancement regions and the isolation junctions through said enhancement openings and said isolation grooves, said first mask and said second mask preventing the diffusant from otherwise entering the semiconductor material;

closing said enhancement openings and said isolation junction grooves by forming diffusant resistant material therein;

removing said second mask from over said collector and emitter contacts; and

diffusing through said emitter and said collector contacts to form conductive connections with said collector and said emitter, said first mask and said diffusant resistant material preventing said collector contact and emitter diffusant from otherwise entering the semiconductor material.

7. The process of claim 6 wherein said step of anisotropically etching said exposed selected areas of the semiconductor material to form said grooves includes applying a potassium hydroxide etch reagent to the semiconductor material, which has a (100) crystallographic orientation.

8. The process of claim 6 wherein the step of providing the collector and emitter contacts respectively in said collector contact grooves and said emitter opening, comprises:

forming a polycrystalline silicon layer in said isolation and collector contact grooves and in said emitter and base enhancement openings and on said first mask;

forming an etch resistant mask over portIons of said polycrystalline silicon layer which overlie the regions of the semiconductor material in which the collector contact and emitter diffusions are to be formed; and

removing said polycrystalline silicon material from said isolation grooves and said base enhancement openings.

9. The process of claim 6 wherein said step of closing said enhancement openings and said isolation junction grooves by forming diffusant-resistant material therein includes forming an additional layer of silicon dioxide therein.

10. A process for forming a silicon semiconductor transistor device having base enhancement and emitter regions each making conductive connection to larger polycrystalline silicon contacts which are all aligned with each other to provide a transistor in semiconductor material having a base with a first surface, and a collector already provided therein, the process comprising:

forming a first mask on the first surface of the base, said first mask having openings which expose selected areas of the base through which the emitter and base enhancement diffusions are to be provided, said step of forming said first mask includes the steps;

forming a first layer of silicon dioxide on the first surface of the base;

forming a first layer of silicon nitride on the first layer of silicon dioxide;

forming a second layer of silicon dioxide on the said first layer of silicon nitride;

etching said second layer of silicon dioxide to form an etch pattern for said underlying first layer of silicon nitride, said first layer of silicon nitride forming an etch stop for said etch of said second layer of silicon dioxide;

etching said silicon nitride to form an etch pattern for said first layer of said silicon dioxide, said first layer of silicon dioxide operating as an etch stop for said etch of said first layer of silicon nitride; and

etching said first layer of silicon dioxide, said base forming an etch stop for said etch of said first layer of silicon dioxide;

providing a layer of polycrystalline silicon over said first mask and in said emitter and base enhancement openings;

forming a second mask over said polycrystalline silicon so that the surface thereof is exposed overlying the base areas wherein said enhancement diffusions are to be performed;

diffusing a boron material through said exposed surfaces of said polycrystalline silicon to transform it into an etch stoppant, and into the base to form the enhancement regions;

removing portions of said second mask between the opening through which the emitter is to be diffused and the openings through which the base enhancements were diffused to thereby expose the underlying polycrystalline silicon material;

etching the polycrystalline silicon material between the edge of the regions of the polycrystalline silicon which were doped by the base enhancement and the edge of the second mask overlying the opening through which the emitter will be diffused to thereby sever the polycrystalline silicon layer to shape the emitter and base contacts, said doped region of polycrystalline silicon material forming an etch stop to protect the base contacts and said second mask forming an etch protective layer to protect the emitter contact from said polycrystalline silicon etch;

providing a third mask over said base contacts;

removing said second mask from over said emitter contact; and

diffusing through said emitter contact to form said emitter, said first and said third masks preventing said emitter diffusant from otherwise entering the semiconductor material.

11. The process of claim 10 wherein said step of forming a second mask over said polycrystalline silicon so that the surfaces thereof are exposed overlying the base areas where said enhancement diffusions are to be performed, includes the steps of forming a second layer of silicon nitride on said polycrystalline silicon;

forming a third layer of silicon dioxide on said second layer of silicon nItride;

selectively etching said third layer of silicon dioxide to provide an etch mask for said second layer of silicon nitride, said first layer of silicon nitride protecting said first layer of silicon dioxide during said etch of said third layer of silicon dioxide; and

etching said second layer of silicon nitride to complete said second mask.

12. The process of claim 10 wherein said step of removing said second mask between the opening through which the emitter is to be diffused and the opening through which the base enhancements were diffused to thereby expose the underlying polycrystalline silicon material includes the step of providing an etch resistant mask on top of said third silicon dioxide layer.