SOLID STATE CONTINUITY CHECK CIRCUIT

• US 3,849,605 A
• Filed: 12/29/1972
• Issued: 11/19/1974
• Est. Priority Date: 12/29/1972
• Status: Expired due to Term

• Current Assignee: Congress Financial Corporation (Wells Fargo & Company)
• Original Assignee: Stanley L. Russell
• Inventors: Russell, Stanley L.
• Primary Examiner(s): Claffy, Kathleen H.
• Assistant Examiner(s): Bartz, C. T.
• Application Number:
  US05/319,245
• Time in Patent Office: 690 Days
• Field of Search: 179/18AB,84A,175.2C,18FA
• US Class Current: 379/9
• CPC Class Codes: H04Q 3/00 Selecting arrangements H04Q5/00 - H04Q11/00 take precedence

Abstract

An optoelectronic coupler, responsive to a check request signal, is connected via a rectifier bridge circuit to the tip and ring lines of a telephone circuit to provide a continuity signal in response to a potential being present across the tip and ring leads. Timing means are provided for transmitting the continuity signal to the system control during a preset time interval in a timing sequence.

Claims

1. A continuity check circuit for common control telephone systems for connection to the tip and ring leads of a telephone circuit for detecting the presence of a potential across the tip and ring leads, said continuity check circuit comprising:

a semiconductor device including an input circuit having a radiation source that generates photon radiation, the intensity of which is a function of the current flow therethrough, and an output circuit having a radiation sensitive device, the impedance of which is a function of the intensity of radiation from said source, said input and output circuits being electrically isolated, and circuit means for connecting, in response to the application thereto of a signal from the common control, said input circuit of said semiconductor device to the tip and ring leads of a telephone circuit so that in response to a potential being present across said tip and ring leads said input circuit is rendered conductive to produce a continuity check signal from said output circuit.

2. A continuity check circuit as defined in claim 1 wherein said circuit means includes:

a rectifier bridge circuit;

switching means for connecting opposite junctions of the bridge circuit across the tip and ring leads, and circuit means for connecting the other opposite junctions of the bridge circuit to said input circuit.

3. A continuity check circuit as defined in claim 2 including:

timing means connected to said output circuit for transmitting the signal from said output circuit for a preset time interval in a timing sequence.

4. A continuity check circuit as defined in claim 3 wherein said timing means includes:

switching circuit means including a flip-flop circuit with a first input circuit connected to said output circuit for enabling the flip-flop circuit to be switched to a first state by said continuity check signal in response to a timing signal applied to a second input circuit of said flip-flop circuit, and to be switched to a second state when said continuity check signal terminates and a second timing signal is applied to said second input circuit of said flip-flop circuit.

5. A continuity check circuit for common control telephone systems for connection to the tip and ring leads of a telephone circuit for detecting the presence of a potential across the tip and ring leads, said continuity check circuit comprising:

an optoelectronic coupler;

a rectifier bridge circuit;

a relay circuit means for connecting opposite junctions of said bridge circuit to the tip and ring leads of a telephone circuit;

circuit means for connecting, in response to the application thereto of a signal from the common control, said optoelectronic coupler to the other opposite junction of said bridge circuit so that said optoelectronic coupler produces a continuity check signal in response to the presence of a potential across the tip and ring leads, and timing means connected to said optoelectronic coupler for repeating the continuity check signal for a preset time interval in a timing sequence.

6. A continuity check circuit as defined in claim 5 wherein said timing means includes:

switching means including a flip-flop circuit with a first input circuit connected to said optoelectronic coupler for enabling the flip-flop circuit to be switched to a first state bY said continuity check signal in response to a timing signal applied to a second input circuit of said flip-flop circuit, and to be switched to a second state when said continuity check signal terminates and a second timing signal is applied to said second input circuit of said flip-flop circuit.

7. A continuity check circuit arrangement for common control telephone systems for connection to a first and a second pair of tip and ring leads extending to at least one telephone circuit for detecting the simultaneous presence of potentials across both of said first pair of tip and ring leads and said second pair of tip and ring leads, said continuity check arrangement comprising:

first and second rectifier bridge circuits;

first and second optoelectronic couplers;

relay circuit means for connecting the opposite junctions within each of said first and second rectifier bridge circuits, respectively, to separate ones of the first and second pairs of said tip and ring leads in response to the application of a signal to said relay circuit means by said common control;

first circuit means connecting the other opposite junctions of the first and second rectifier bridge circuits to separate ones of said first and second optoelectronic couplers so that in response to potentials applied across the tip and ring pairs, corresponding optoelectronic couplers produce continuity check signals, and second circuit means responsive to the simultaneous presence of the continuity check signals from said first and second optoelectronic couplers to provide a signal indicating a valid connection.

8. The continuity check arrangement as defined in claim 7 including:

timing means connected to said second circuit means for repeating the valid connection signal at a preset time slot in a timing sequence.