MULTI-DIMENSIONAL PATTERN RECOGNITION PROCESSOR
First Claim
1. A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of individual picture elements of a multi-dimensional original pattern, a mask register unit for designating a multi-dimensional weight information pattern applied to the pattern information of the individual picture elements of the original pattern, a plurality of multiplier groups for simultaneously carrying out the multiplication on all the picture elements of the original pattern such that pattern information signals representative of the picture elements of the original pattern derived from said pattern data register unit are multiplied by weight information signals derived from the corresponding picture element portions of said mask register unit, and a plurality of adders each associated with one of said multiplier groups for carrying out the addition of the results of multiplication by said multiplier groups, wherein weight information stored in said mask register unit is changed to various forms so that said original pattern information can be suitably processed depending on said changed weight information.
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Abstract
A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of a multidimensional original pattern, a weight register unit for applying weight information to the original pattern information, and a filtering logic arithmetic unit for carrying out predetermined arithmetic operations (filtering logic) on the original pattern information and weight information stored in and supplied from the respective register units. In the processor, various weight information are employed so as to carry out (1) space coordinate transformation such as rotation, expansion or contraction of the multi-dimensional original pattern, (2) operation for seeking the correlation between the multi-dimensional original pattern and a standard pattern, (3) detection of the geometrical features of the multi-dimensional original pattern, or (4) extraction of the features as to the color and tone of the multi-dimensional original pattern.
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Citations
7 Claims
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1. A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of individual picture elements of a multi-dimensional original pattern, a mask register unit for designating a multi-dimensional weight information pattern applied to the pattern information of the individual picture elements of the original pattern, a plurality of multiplier groups for simultaneously carrying out the multiplication on all the picture elements of the original pattern such that pattern information signals representative of the picture elements of the original pattern derived from said pattern data register unit are multiplied by weight information signals derived from the corresponding picture element portions of said mask register unit, and a plurality of adders each associated with one of said multiplier groups for carrying out the addition of the results of multiplication by said multiplier groups, wherein weight information stored in said mask register unit is changed to various forms so that said original pattern information can be suitably processed depending on said changed weight information.
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2. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein a non-linear arithmetic unit is additionally provided for selecting solely the signals having a level higher than a predetermined threshold value from the output signals of said adders.
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3. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein said weight information pattern comprises a plurality of picture elements lying along one diagonal of a square and lying along a partial circle drawn around one of the ends of said diagonal so as to pass through the center of said square, and a plurality of picture elements adjoining to said picture elements along said diagonal and said partial circle, said partial circle being defined in the area of said square.
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4. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein said weight information pattern comprises a plurality of picture elements arranged in the shape of a square with at least one picture element added to a side of said square.
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5. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein said weight information pattern comprises a plurality of picture elements arranged in a square with at least one picture element added to each of two sides of the square and at least one additional picture element added to at least one corner of the square in the direction of a diagonal of the square.
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6. A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of indIvidual picture elements of a multi-dimensional original pattern, a mask register unit for designating the weight applied to the pattern information of the individual picture elements of the original pattern, a plurality of hybrid multiplier groups connected to said register units for computing the product of two input signals representative of a multiplier and a multiplicant one of which is a digital signal and the other of which is an analog signal, a plurality of analog adder groups each connected to one of said hybrid multiplier groups for carrying out the addition of an addend and a summand both of which are analog signals, and a group of analog to digital converters each converting the analog output signal of one of said adder groups into a digital signal, wherein the weight information stored in said mask register unit is changed to various forms so that said pattern information can be suitably processed depending on said changed weight information.
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7. A multi-dimensional pattern recognition processor as claimed in claim 6, wherein a non-linear arithmetic unit is connected between said analog adder groups and said analog to digital converter group so as to select solely the analog signals having a level higher than a predetermined threshold value from the analog output signals of said analog adder groups.
Specification