MULTIPLE PULSE REPETITION FREQUENCY DECODER

• US 3,851,261 A
• Filed: 06/21/1973
• Issued: 11/26/1974
• Est. Priority Date: 06/21/1973
• Status: Expired due to Term

• Current Assignee: Timothy F. Geiger
• Original Assignee: Timothy F. Geiger
• Inventors: Geiger, Timothy F.
• Primary Examiner(s): Krawczewicz, Stanley T.
• Application Number:
  US05/372,139
• Time in Patent Office: 523 Days
• Field of Search: 324/77R,77B,77H,78D 328/165,138
• US Class Current: 327/114
• CPC Class Codes: H03K 3/013 Modifications of generator to prevent operation by noise or interference

Abstract

An input signal is comprised of a maximum number of known pulse repetition frequencies. In order to determine which frequency components are present, the input signal is fed to a shift register network. Each frequency component may be decoded when preselected stages of the register network simultaneously store pulses of a particular frequency component, and by parallel feeding the outputs of these stages to a respective coincidence gate, an output is generated at the gate that indicates the presence of the respective frequency component.

Claims

1. A system for decoding known components of an input signal having multiple pulse repetition frequencies, the system comprising:

shift register means having its input connected to the signal for shifting the input signal therethrough, the pulses of respective components being stored in different stages of the shift register means at the end of a plurality of cycles of a clock connected to the shift register means;

coincidence means respectively connected to a plurality of preselected stages of the shift register means for becoming enabled at the end of a plurality of cycles, said enablement causing the generation of signals indicative of respective components;

wherein the shift register means comprises a first shift register connected to the input signal and having a number of stages equal to the quantity period of highest frequency signal/period of clock - 1;

a second shift register having its input connected to the last stage of the first shift register, the stage capacity of the second shift register equal to the number of frequency components, the second shift register further being clocked with additional pulses for circulation;

a third shift register having the same stage capacity as the first shift register and being clocked at the same rate as the first shift register;

a jumper lead for connecting the last stage of the first shift register to the input of the third shift register;

a fourth shift register having its input connected to the last stage of the third shift register and a stage capacity equal to twice the number of frequency components, the fourth shift register being circulated at a rate equal to twice the circulation rate of the second shift register; and

further wherein said coincidence means comprises a plurality of coincidence gates equal in number to the components; and

means for connecting preselected stages of the second and fourth shift registers to the gates for enabling the gates in response to the presence of the frequency components in the input signal.

2. A system for decoding known components of an input signal having multiple pulse repetition frequencies, the system comprising:

shift register means having its input connected to the signal for shifting the input signal therethrough, the pulses of respective components being stored in different stages of the shift register means at the end of a plurality of cycles of a clock connected to the shift register means;

coincidence means respectively connected to a plurality of preselected stages of the shift register means for becoming enabled at the end of a plurality of cycles, said enablement causing the generation of signals indicative of respective components;

wherein the shift register means comprises a first shift register connected to the input signal and having a number of stages equal to period of highest frequency signal/period of clock - 1;

a second shift register having its input connected to the last stage of the first shift register, the stage capacity of the second shift register equal to the number of frequency components, the second shift register further being clocked with additional pulses for circulation;

a third shift register having the same stage capacity as the first shift register and being clocked at the same rate at the first shift register;

means for connecting the last stage of the first shift register to the first stage of the third shift register;

a fourth shift register having an input connected to the last stage of the third shift register and further having a stage capacity equal to twice the number of frequency components and a circulation rate equal to twice the circulation rate of the second shift register; and

individual feedback means connected between the respective last stage of the second and fourth shift registers and the input thereof to create recirculation of datA in the second and the fourth shift registers; and

means connecting the last stages of the second and fourth shift register to said coincidence means that particularly includes a single coincidence gate; and

means connecting the input signal to the coincidence gate;

wherein the input signal flows between the first and third shift registers at the same clocking rate, the last stage of the first and third shift registers being respectively connected to the second and fourth shift registers which provide additional stage capacity between each cycle of the clock associated with the first and third shift register, the second and fourth shift registers being completely cycled once during each primary clock cycle, and the data stored by the second and fourth shift registers being compared with the input signal at the coincidence gate, the gate being enabled when three consecutive pulses of an expected frequency component occurs.