DUAL-MODE SECURITY CIRCUIT FOR AUTOMOTIVE VEHICLES AND THE LIKE

• US 3,852,614 A
• Filed: 11/23/1973
• Issued: 12/03/1974
• Est. Priority Date: 11/23/1973
• Status: Expired due to Term

• Current Assignee: Cooper Industries, Inc. (Eaton Corporation PLC.)
• Original Assignee: Paul A. Carlson
• Inventors: Carlson, Paul A.
• Primary Examiner(s): Schaffer, Robert K.
• Assistant Examiner(s): Ginsburg, M.
• Application Number:
  US05/418,683
• Time in Patent Office: 375 Days
• Field of Search: 307/1R,1AT 340/63,64 180/114,112
• US Class Current: 307/10.2
• CPC Class Codes: B60R 25/04 operating on the propulsion system, e.g. engine or drive motor
• CPC Class Codes: B60R 25/22 using mechanical identifiers
• CPC Class Codes: B60R 25/24 using electronic identifiers containing a code not memorised by the user

Abstract

A security circuit electronically switchable between a first (key) mode in which the engine starting circuit may be activated by means of a mechanically-keyable switch alone, and a second (security) mode in which the activation of the engine starting circuit may be carried out within a predetermined period of time by means of a mechanically-keyable switch only after a predetermined signal has been provided to the security circuit in response to an electronic key. The security circuit is also operative to open the vehicle door locks in response to the electronic key, and will subsequently reclose all of the locks if the vehicle is not entered within a predetermined period of time. When the operator gains entry to the vehicle by means of the electronic key, all of the vehicle doors will be automatically locked when the operator closes the door through which he entered.

Claims

1. In a vehicle comprising a keyable control means operative when keyed to generate a control signal, a multi-position ignition switch having at least OFF, ON and START positions, at least one door switch, at least one door lock/unlock means, and engine starting means, the improvement comprising:

dual-mode security circuit means operative in the security mode in response to said control signal (1) to actuate said at least one door lock/unlock means so as to unlock the associated door and (2) to enable energization of said engine starting means by actuation of said multi-position ignition switch to the START position within a predetermined period of time after the actuation and deactuation of said at least one door switch, said dual-mode security circuit means being switched to the key mode of operation upon actuation of said at least one door switch and subsequent generation of said control signal, said dual-mode security circuit means being operative in the key mode to enable energization of saiD engine starting means by actuation of said multi-position ignition switch to the START position, said dualmode security circuit means being switched back to the security mode by generation of said control signal.

2. memory latching circuit means operative to receive said first enabling signal from said memory circuit means and to produce an intermediate signal in response thereto;

3. The improvement according to claim 1 wherein said dual-mode security circuit means is further operative to actuate said at least one door lock/unlock means so as to lock the associated door in response to the actuation and de-actuation of said at least one door switch.

4. unlocking circuit means operative to receive said control signal and, in response thereto, to generate and apply a door unlock signal to said at least one door lock/unlock means so as to unlock the associated door;

5. The improvement according to claim 1 wherein said dual-mode security circuit means is further operative to provide first and second signals indicating operation in either the security mode or the key mode, respectively.

6. mode selector circuit means operative to receive a signal from said at least one door switch and said control signal, and further operative in response to the occurrence of said door switch and control signals in that order to switch said dual-mode security circuit means to the key mode of operation, said mode selector circuit means then being operative to generate and apply a third enabling signal to said memory latching circuit means each time said at least one door switch is actuated, and being further operative to receive said control signal and, in response thereto, to switch said dual-mode security circuit means to the Security mode.

7. The improvement according to claim 1 wherein said keyable control means is electronically keyable, and said multi-position ignition switch is actuatable without any key.

8. The improvement according to claim 1 wherein said keyable control means is mechanically keyable by means of a first key, and said multi-position ignition switch is mechanically keyable by means of a second key.

9. The improvement according to claim 1 wherein said keyable control means is mechanically keyable, and said multi-position ignition switch is actuatable without any key.

10. The improvement according to claim 1 wherein said dual-mode security circuit means comprises:

11. The improvement according to claim 10 wherein said dual-mode security circuit means further comprises locking circuit means operative in response to the actuation and de-actuation of said at least one door switch to generate and apply a door lock signal to said at least one door lock/unlock means so as to lock the associated door.

12. The improvement according to claim 11 wherein said locking circuit means is further operative to delay the actuation of said at least one door lock/unlock means so as to lock the associated door a predetermined period of time after actuation and de-actuation of said at least one door switch.

13. The improvement according to claim 11 wherein said mode selector circuit means is further operative, when said dual-mode security circuit means is in the key mode, to generate and apply a disabling signal to said locking circuit means which, in response thereto, is disabled from generating a door lock signal.

14. The improvement according to claim 11 wherein said dual-mode security circuit means further comprises relock circuit means operative to receive a priming signal from said driver circuit means and operative upon termination of said priming signal to generate and apply a relock signal to said locking circuit means which, in response thereto, is operative to generate and apply a door lock signal to said at least one door lock/unlock means so as to relock the associated door if said at least one door switch is not actuated within a predetermined period of time from the termination of said control signal.

15. The improvement according to claim 14 wherein said locking circuit means is further operative to generate and apply a latching signal to said relock circuit means to prevent said relock circuit means from generating said relock signal when said locking circuit means is generating said door lock signal in response to actuation and de-actuation of said at least one door switch.

16. The improvement according to claim 10 wherein said dual-mode security circuit means further comprises mode indicator circuit means operative to receive first and second mode signals from said mode selector circuit means and, in response thereto, to provide first and second signals indicating operation in either the key mode or the security mode, respectively.

17. The improvement according to claim 16 wherein energization of said mode indicator circuit means is controlled by said at least one door switch, said mode indicator circuit means being energized when said at least one door switch is actuated and de-energized when said at least one door switch is de-actuated.

18. The improvement according to claim 10 wherein said memory circuit means comprises a resistance and a capacitance connected in parallel with one another and in series through a diode to said keyable control means to receive the control signal therefrom, said first enabling signal being developed across said capacitance.

19. The improvement according to claim 10 wherein said memory latching circuit means comprises:

1 first and second inverters connected in series with one another between the output of said memory circuit means and the input to said driver circuit means;

2 a NAND gate having one input connected to the output of said second inverter and the other input connected to receive a signal generated by said mode selector circuit means in response to the actuation of said at least one door switch; and

3 a third inverter connected between the output of said first NAND gate and through a diode to the input of said first inverter.

20. The improvement according to claim 10 wherein said driver circuit means comprises:

1 a first transistor coupled to and controlled by the output of said memory latching circuit means;

2 a second transistor having its turn-on current path controlled by said first transistor; and

3 a third transistor having its turn-on current path controlled by said second Transistor, and operative when rendered conductive to enable energization of said engine starting means by actuation of said multi-position ignition switch to the START position.

21. The improvement according to claim 10 wherein said unlocking circuit means comprises:

1 a first inverter coupled to said keyable control means to receive said control signal therefrom;

2 a resistance and a capacitance connected in series between a source of power and the output of said first inverter;

3 a second inverter having its input connected to the junction of said resistance and said capacitance; and

4 driver circuit means connected to and controlled by the output of said second inverter, said driver circuit means being operative to generate said door unlock signal when the output of said second inverter is high.

22. The improvement according to claim 21 wherein said capacitance is normally charged, and is discharged when the output of said first inverter goes low in response to said control signal, and is recharged through said resistance after the output of said first inverter again goes high, the low output of said first inverter being effectively transmitted through said discharged capacitance to the input of said second inverter so that the output of said second inverter goes high until said capacitance is recharged to a level above the input threshold of said second inverter.

23. The improvement according to claim 10 wherein said ignition latching circuit means comprises:

1 a voltage divider comprising first and second resistances connected in series from the ON terminal of said multi-position ignition switch to ground;

2 a NAND gate having a first input connected through a first diode to the junction of said first and second resistances and the second input coupled to said at least one door switch; and

3 an inverter and a second diode connected in series from the output of said NAND gate to said first input of said NAND gate and to said memory latching circuit means, said second enabling signal being developed at one terminal of said second diode.

24. The improvement according to claim 23 wherein said ignition latching circuit means further comprises a filtering network comprising a third resistance and a capacitance connected in parallel with one another between said first input of said NAND gate and ground.

25. The improvement according to claim 10 wherein said mode selector circuit means comprises:

1 a voltage divider comprising first and second resistances connected in series with one another and in parallel with said at least one door switch;

2 a first inverter having its input connected to the junction of said first and second resistances;

3 latching/unlatching circuit means operative to receive said control signal, said door switch signal in the form of the voltage developed at the junction of said first and second resistances, and the output of said first inverter, and further operative in response to the occurrence of said door switch and control signals in that order to generate a high output which is latched on after the termination of said door switch and control signals, and being further operative to receive said control signal and, in response thereto, to unlatch said high output and generate a low output; and

4 output means operative in response to the high output of said first inverter and the high output of said latching/unlatching circuit means to generate and apply said third enabling signal to said memory latching circuit means.

26. The improvement according to claim 25 wherein said output means comprises:

1 a NAND gate having a first input connected to the output of said latching/unlatching circuit means and a second input connected to the output of said first inverter; and

2 a second inverter having its input connected to the output of said NAND gate, said third enabling signal being dEveloped at the output of said second inverter when the output of said NAND gate is low.

27. The improvement according to claim 11 wherein said locking circuit means comprises:

1 a first resistance and a first capacitance connected in series with one another across the terminal of a source of power;

2 a first inverter having its input connected to the junction of said first resistance and said first capacitance and through a diode to the high side of said at least one door switch;

3 a second resistance and a second capacitance connected in series between a source of power and the output terminal of said first inverter;

4 a second inverter having its input connected to the junction of said second resistance and said second capacitance; and

5 driver circuit means coupled to and controlled by the output of said second inverter, and being operative to generate said door lock signal in response to a high output from said second inverter.

28. The improvement according to claim 27 wherein said first and second capacitances are normally charged, and said first capacitance is discharged through said diode upon actuation of said at least one door switch, in response to which the output of said first inverter goes high, effectively discharging said second capacitance, said first capacitance being recharged through said first resistance upon de-actuation of said at least one door switch, the output of said first inverter being driven low after said first capacitance has recharged to a voltage above the input threshold of said first inverter, the low output of said first inverter being applied through said discharged second capacitance to the input of said second inverter to cause the output of said second inverter to go low until said second capacitance has recharged to a voltage above the input threshold of said second inverter.

29. The improvement according to claim 14 wherein said relock circuit means comprises:

1 a first inverter connected to said driver circuit means to receive said priming signal therefrom;

2 a second inverter having its input connected to the output of said first inverter;

3 a first resistance and a first capacitance connected in series between a source of power and the output of said second inverter;

4 a third inverter having its input connected to the junction of said first resistance and said first capacitance;

5 a first NAND gate having a first input connected to the output of said third inverter;

6 a fourth inverter having its input connected to the output of said first NAND gate and operative to generate said relock signal in response to a low output from said first NAND gate; and

7 disabling circuit means operative to receive said priming signal and a latching signal from said locking circuit means, and further operative in response thereto to generate a second input to said first NAND gate to prevent the generation of said relock signal.

30. The improvement according to claim 29 wherein said disabling circuit means comprises:

1 a second NAND gate having its output connected to said second input of said first NAND gate;

2 a fifth inverter having its input connected to the output of said second NAND gate, and having its output coupled to a first input of said second NAND gate;

3 a second resistance and a second capacitance connected in parallel with one another from a second input of said second NAND gate, said second capacitance being operative to receive said priming signal; and

4 coupling circuit means operative to transmit said latching signal from said locking circuit means to said first input of said second NAND gate.

31. The improvement according to claim 30 wherein the period of time required for the discharge of said second capacitance through said second resistance to a level below the input threshold of said second NAND gate is greater than the period of time required for the recharging of said first capacitance through said first resistance to a level above the input threshold of said third inverter after the output of said second inverter goes high and low.

32. A dual-mode control circuit comprising:

1 enabling circuit means operative to receive a control signal and, in response thereto, to enable energization of a load for a predetermined period of time after termination of said control signal;

2 latching circuit means operative in response to the energization of a load to generate and apply an enabling signal to said enabling circuit means as long as the load remains energized; and

3 mode selector circuit means operative to receive a predetermined input signal and said control signal, and further operative in response to the occurrence of said predetermined input and control signals in that order to switch said dual-mode control circuit to a first mode of operation, said mode selector circuit means then being operative to generate and apply an enabling signal to said enabling circuit means each time said predetermined input signal is received, and being further operative to receive said control signal and, in response thereto, to switch said dual-mode control circuit to a second mode of operation in which said mode selector circuit means is disabled from generating and applying said enabling signal to said enabling circuit means in response to said predetermined input signal.