CONTROL HAVING CONDUCTION LIMIT MEANS TO VARY DUTY CYCLE OF POWER SWITCH

• US 3,855,520 A
• Filed: 12/22/1972
• Issued: 12/17/1974
• Est. Priority Date: 12/22/1972
• Status: Expired due to Term

• Current Assignee: AC Material Handling Corporation
• Original Assignee: Frederick A. Stich
• Inventors: Stich, Frederick A.
• Primary Examiner(s): Pellinen, A. D.
• Application Number:
  US05/317,596
• Time in Patent Office: 725 Days
• Field of Search: 307/237,240,254,296 317/31 318/139,333,341 321/2 323/17,19,22T,23,38,DIG.1
• US Class Current: 323/283
• CPC Class Codes: H02P 7/29 using pulse modulation
• CPC Class Codes: Y10S 388/903 Protective, e.g. voltage or current limit
• CPC Class Codes: Y10S 388/921 Timer or time delay means

Abstract

A pulse width modulation control for supplying variable width voltage pulses from a battery to a motor includes a power switch, an oscillator for providing a succession of triggering pulses, a monostable multivibrator operated by each triggering pulse to generate a rectangular guard pulse, a bistable logic gate latch triggered by each guard pulse to a first condition wherein it generates a control signal to turn on the power switch, a variable delay circuit operated by each triggering pulse to initiate a timing interval and to provide a timing signal after a selectively variable time delay which triggers the bistable latch to a second condition wherein it removes the control signal to thereby turn off the power switch, a conduction limit circuit which senses the collector-to-emitter voltage across the power switch and generates a conduction limit signal when the power switch comes out of saturation, a first logic gate between the bistable latch and the power switch which, when enabled, transmits the control signal to turn on the power switch, and a second logic gate which is operated by the conduction limit signal in the absence of a guard pulse to disable the first gate to thus turn off the power switch and reduce the duty cycle of each voltage pulse and is operated by each guard pulse to enable the first gate and thus permit the power switch to turn on at the beginning of each voltage pulse.

Claims

1. A control for supplying variable duty cycle pulses from an electrical power source to a load including, in combination, means for providing a succession of control pulses, means for selectively varying the duty cycle of said control pulses, a power switch regulated by said control pulses for connecting said power source to said load, conduction limit means for sensing the voltage across said power switch and for generating a conduction limit signal when said voltage exceeds a predetermined magnitude, and means responsive to said conduction limit signal for overriding said duty cycle varying means and reducing the duty cycle of said control pulses.

2. A control in accordance with claim 1 wherein said means to reduce the duty cycle of said control pulses includes means for generating a narrow guard pulse at the leading edge of each of said control pulses, and means responsive to each said guard pulse to turn on said power switch and being responsive to said conduction limit signal in the absence of said guard pulse to terminate each said control pulse and thereby turn off said power switch.

3. A control in accordance with claim 2 wherein said means responsive to each said guard pulse to turn on said power switch incluDes logic gate means receiving said control pulses and being adapted when enabled to transmit said control pulses to said power switch, means responsive to said conduction limit signal in the absence of said guard pulse to disable said logic gate means and thereby block transmission of said control pulses, and conduction limit defeating means responsive to said guard pulse to disable said last-named means.

4. In a control in accordance with claim 2 wherein said power switch includes a plurality of paralleled power transistors each of which has a forward current transfer ratio versus collector current characteristic with a portion wherein said ratio decreases abruptly with increase of collector current, said control includes means regulated by said control pulses for supplying substantially constant base drive to said power transistors of sufficient magnitude so that they operate on said portion wherein said ratio decreases abruptly with increase of collector current, and said conduction limit means senses the collector-to-emitter voltage across said paralleled power transistors.

5. A control in accordance with claim 1 wherein said means for overriding said duty cycle varying means includes means for generating a narrow guard pulse at the leading edge of each control pulse, means responsive to said conduction limit signal to terminate each said control pulse and thereby turn off said power switch, and means responsive to each said guard pulse to disable said last-named means.

6. A control in accordance with claim 5 wherein said means to terminate each said control pulse includes first logic gate means adapted when enabled and disabled respectively to transmit and block said control pulses to said power switch, and said means to disable said last-named means includes second logic gate means for controlling said first logic gate means and receiving said guard pulses and said conduction limit signal as inputs and being operated by each said guard pulse to enable said first logic gate means and being operated by said conduction limit signal in the absence of a guard pulse to disable said first logic gate means, said second logic gate means being nonresponsive to said conduction limit signal when a guard pulse is present.

7. A control in accordance with claim 1 including means for generating a narrow guard pulse at the leading edge of each of said control pulses, and means responsive to each said guard pulse to disable said duty cycle reducing means.

8. A control in accordance with claim 7 wherein said means for providing a succession of control pulses includes logic means for transmitting said control pulses to said power switch and being responsive to said conduction limit signal in the absence of a guard pulse to terminate said control pulse and thereby turn off said power switch, said logic means receiving said guard pulses as an input and being disabled by each guard pulse from responding to said conduction limit signal, whereby the conduction limit means is defeated during said guard pulse to permit said power switch to turn on.

9. A control in accordance with claim 8 wherein said means for providing a succession of control pulses includes means for providing a train of triggering pulses, variable delay means operated by each triggering pulse to provide a timing signal after a selectively variable time delay, said guard pulse generating means including a guard pulse monostable multivibrator which is operated to its unstable state by each said triggering pulses to derive a guard pulse, and wherein said logic means includes a bistable latch which is set by each guard pulse to establish the leading edge of a control pulse and is reset by each timing signal to establish the trailing edge of said control pulse.

10. A control in accordance with claim 8 wherein said guard pulse generating means includes a guard pulse monostable multivibrator which is operated to its unstable state at the leading edge of each of said control pulses.

11. A control in accordance with claim 1 and including base drive means for applying base drive to said power switch of sufficient magnitude to drive it into saturation, said base drive means being controlled by said control pulses.

12. A control in accordance with claim 1 wherein said means for providing a succession of control pulses and said means for varying the duty cycle thereof includes means for generating a train of narrow triggering pulses, variable delay means actuated by each triggering pulse to provide a timing signal after a selectively variable time delay, and bistable latch means set in response to said triggering pulses to establish the leading edge of said control pulses and reset in response to said timing pulses to establish the trailing edge of said control pulses.

13. A control in accordance with claim 12 wherein said duty cycle reducing means includes logic gate means between said bistable latch means and said power switch receiving the output of said latch means and being enabled and disabled to transmit and block said control pulses respectively when said latch means is set and reset and receiving said conduction limit signal as an input and being disabled by said conduction limit signal to block transmission of said control pulse.

14. A control in accordance with claim 13 and including means responsive to each said triggering pulse for preventing the disabling of said logic gate means for a predetermined time interval of sufficient duration to permit said power switch to turn on.

15. A control for applying variable duty cycle voltage pulses from an electrical power source to a load comprising, in combination, means for providing a succession of triggering pulses, a power switch of the transistor type in series with said power source and said load, variable delay means operated by each of said triggering pulses for providing a timing signal after a selectively variable time delay, conduction limit means for sensing the collector-to-emitter voltage across said power switch and for generating a conduction limit signal when said voltage exceeds a predetermined magnitude, means operated by each of said triggering pulses for turning on said power switch and operated by said timing signal to turn off said power switch so that said power switch applies variable duty cycle voltage pulses from said source to said load, and means responsive to said conduction limit signal to operate said last-named means to turn off said power switch and thereby reduce the duty cycle of said voltage pulses.

16. A control in accordance with claim 15 wherein said means to reduce the duty cycle of said voltage pulses turns off said power switch to terminate said voltage pulses, and said control includes conduction limit defeating means to disable said duty cycle reducing means during the duration of each of said triggering pulses.

17. A control in accordance with claim 16 wherein said power switch includes a plurality of paralleled transistors each of which has a forward current transfer ratio versus collector current characteristic wherein said ratio decreases abruptly with increase in collector current, and said means for turning on said power switch includes means for supplying substantially constant base drive current to said paralleled transistors.

18. A control in accordance with claim 16 wherein said means for turning said power switch on and off includes bistable latch means operated to a first condition by each said triggering pulse to initiate a control signal and operated to a second condition by said timing signal to terminate said control signal, and wherein said power switch is controlled by said control signals.

19. A control in accordance with claim 18 wherein said means to reduce the duty cycle of said voltage pulses includes logic gate means between said bistable latch means and said power switch adapted when enabled and disabled respectively to transmIt and to terminate said control signal, and means receiving said triggering pulses and said conduction limit signal as inputs operated by each of said triggering pulses to enable said logic gate means and operated by said conduction limit signal in the absence of a triggering pulse to disable said logic gate means and being nonresponsive to said conduction limit signal when said triggering pulse is present.

20. In a control in accordance with claim 18 wherein said variable delay means is controlled by a speed potentiometer and including means responsive to a predetermined low resistance setting of said speed potentiometer for holding said bistable latch means in said second condition.

21. A control for supplying variable time ratio pulses from an electrical power source to a load including, in combination, a power switch of the transistor type between said source and said load, means for providing a succession of triggering pulses, variable delay means operated by each said triggering pulse for providing a timing signal after a selectively variable time delay, conduction limit means for providing a conduction limit signal when the collector-to-emitter voltage across said power switch exceeds a predetermined magnitude, bistable latch means operated to a first condition by each said triggering pulse to initiate a control signal to turn on said power switch and operated to a second condition by said timing signal to terminate said control signal, logic gate means between said latch means and said power switch for transmitting and blocking said control signal when enabled and disabled respectively, said logic gate means being enabled and disabled when said latch means is respectively in said first and second conditions and also being disabled by said conduction limit signal in the absence of a triggering pulse, and means responsive to said triggering pulse to prevent said logic gate means from responding to said conduction limit signal.

22. A control in accordance with claim 21 wherein said power switch includes a plurality of paralleled transistors each of which has a forward current transfer ratio versus collector current characteristic with a portion wherein said ratio decreases abruptly with increase of collector current, and including base drive means regulated by said control signal for applying substantially constant base drive current of sufficient magnitude to said transistors so that they operate in saturation on said portion wherein said ratio decreases abruptly with increase of collector current.

23. In a control in accordance with claim 22 wherein each of transistors is of the type which may operate in the active region for a predetermined time interval without failure, and said means for providing a succession of triggering pulses includes a monostable multivibrator which generates triggering pulses whose duration is greater than said predetermined interval.

24. In a control in accordance with claim 21 wherein said variable delay means is controlled by a speed potentiometer, and including means for generating a low resistance signal when the resistance of said speed potentiometer is below a predetermined value, and wherein said bistable latch means is held in said second condition by said low resistance signal.

25. A control for supplying variable time ratio pulses from an electrical power source to a load comprising, in combination, a power switch between said source and said load comprising a plurality of paralleled power transistors of the type whose forward current transfer ratio decreases abruptly with increase of collector current, means for supplying substantially constant base drive to said power switch, an oscillator for providing a succession of triggering pulses, a monostable multivibrator triggered by each oscillator output pulse to generate a rectangular guard pulse, variable delay means operated by each said triggering pulse to provide a timing signal after a selectiVely variable time delay, conduction limit means for providing a conduction limit signal when the collector-to-emitter voltage across said power switch exceeds a predetermined magnitude, bistable latch means triggered to a first condition by each said guard pulse to initiate a control signal to turn on said base drive current supplying means and triggered to a second condition by said timing signal to remove said control signal, and logic gate means between said latch means and said base drive current supplying means adapted when enabled and disabled to respectively transmit and block said control signal, said logic gate means being enabled and disabled when said bistable latch means is respectively in said first and second conditions and also being disabled by said conduction limit signal in the absence of a guard pulse, and conduction limit defeating means responsive to said guard pulse for preventing the disabling of said logic gate means.

26. A variable time ratio control for supplying variable duty cycle pulses from an electrical power source to a load comprising, in combination, means for providing a succession of control pulses, means for providing a narrow pulse at the leading edge of each control pulse, a transistor power switch controlled by said control pulses for connecting said power source to said load, duty cycle varying means for selectively varying the duty cycle of said control pulses, sensing means for providing a limit signal when the collector-to-emitter voltage across said transistor power switch exceeds a predetermined magnitude, conduction limit means responsive to said limit signal for overriding said duty cycle varying means and reducing the duty cycle of said control pulses, and means responsive to each said narrow pulse to defeat said conduction limit means.

27. A control in accordance with claim 26 wherein said means for providing a narrow pulse includes monostable multivibrator means for providing a narrow guard pulse of constant width at the leading edge of each of said control pulses, and logic means receiving said control pulses and said guard pulses and said limit signals as inputs for transmitting said control pulses to said power switch and being responsive to said limit signal in the absence of a guard pulse to block transmission of said control pulses and being nonresponsive to said limit signal when said guard pulse is present.