ASYNCHRONOUS INTERNALLY CLOCKED SEQUENTIAL DIGITAL WORD DETECTOR

• US 3,855,576 A
• Filed: 05/29/1973
• Issued: 12/17/1974
• Est. Priority Date: 05/29/1973
• Status: Expired due to Term

• Current Assignee: Eugene J. Bruckert, Gerald L. Giacomino, Phillip Partipilo, William V. Braun
• Original Assignee: Eugene J. Bruckert, Gerald L. Giacomino, Phillip Partipilo, William V. Braun
• Inventors: Braun, William V., Bruckert, Eugene J., Giacomino, Gerald L., Partipilo, Phillip
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/364,988
• Time in Patent Office: 567 Days
• Field of Search: 235/181 340/146.2,146.3Q,146.3WD,146.3Z,149R,167R
• US Class Current: 708/212
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04W 88/026 using digital address codes
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A detector for detecting predetermined digital words within a train of signals wherein the digits in the words each have a predetermined time period. The detector continuously samples the train of signals coupled thereto. Samplings are taken a number of times during the interval of a digit time period, and a digital signal corresponding to the sampled signal for each sample taken is stored in a multi-stage storage register. Comparison circuitry compares the digital signals in the storage register with a first predetermined word in a memory circuit. If there is a correlation, the comparison circuit counts for a time period long enough to sample the train of signals and store a new series of signals corresponding to a second digital word. The comparison circuit compares these second digital signals with a second word in the memory circuit. A correlation between theset two words produces a detection signal. A signal correlator is also employed which samples the digital signals in the storage register and compares them to determine whether the signals constitute signal information or noise. If noise is detected, the correlator terminates the deteector and associated receiver operation for a predetermined period of time then re-energizes and again checks for the presence of signal information.

Claims

1. A detector for detecting first and seocnd predetermined digital words within a train of signals wherein the digits in said words each have a predetermined time period, said detector including in combination;

clock means for developing a plurality of first clOck pulses during the interval of one of said digit time periods, sample and storage means for receiving said train of signals, said sample and storage means being coupled to said clock means and responsive to each of said first clock pulses to sample the signals in said train of signals coupled thereto and store a digital signal corresponding to said sampled signal, memory means for storing digital words corresponding to said predetermined digital words, and comparison means coupled to said sample and storage means and said memory means and operative between said first clock pulses to compare said digital signals in said sample and storage means with a first digital word in said memory means, said comparison means being operative in response to a correlation between said digital signals in said sample and storage means and said first digital word to count a first time period at least as long as the time period of the second digital word and develop a first timing signal, said comparison means being further operative in response to said first timing signal to compare the digital signals in said sample and storage means with the second digital word in said memory means and develop a detection signal in response to a correlation therebetween.

2. The detector of claim 1 wherein said predetermined digital words each include a plurality of said digits, and said sample and storage means includes a plurality of storage stages equal to the number of said digits in one of said words multiplied by the plurality of first clock pulses developed during the interval of one of said digit time periods.

3. The detector of claim 2 wherein said comparison means includes first gating circuit means coupled to said sample and storage means and said memory means and operative to compare said digital signals in said sample and storage means with said first digital words in said memory means and develop comparison signals in response to a comparison therebetween, counter means coupled to said first gating circuit means for counting said comparison signals, said counter means developing counting signals in response to said comparison signals indicative of a predetermined number of miscorrelations, circuit means operative in response to particular counting signals to switch from a first mode select signal to a second mode select signal, said counter means operative in response to said second mode select signal to inhibit counting said comparison signals, to count for at least said first time period and develop said first timing signal, said memory means being operative in response to said second mode select signal to couple said second digital word to said comparison means, said circuit means being operative in response to said first timing signal to develop a reset mode select signal, said counter means operative in response to said reset mode select signal to count said comparison signals coupled thereto and develop counting signals indicative of a predetermined number of miscorrelations between said second digital word and said digital signals in aid sample and storage means, said circuit means operative in response to said particular counting signals to develop said detection signal.

4. The detector of claim 3 wherein said circuit means further includes, timing means coupled to said counter means and operative in response to said first timing signal to develop a second timing signal of a predetermined period, and second gating circuit means coupled to said counter means and timing means and being operative in response to said second timing signal and said counting signals indicative of said predetermined number of miscorrelations between said second digital word and said digital signals to develop said detection signal.

5. The detector of claim 4 wherein said digital signals are binary signals, said digits are bits, snd said digital words are binary words.

6. The detector of claim 5 wherein said clock means includes means for developing third clock pulses, divider means coupled to sAid means for developing said third clock pulses, said divider means being operative to divide said third clock pulses by a first particular number to develop said second clock pulses, said divider means being operative to divide by a second particular number larger than said first particular number and develop first clock pulses.

7. The detector of claim 6 wherein said sample and storage means includes first shift register means having said plurality of storage stages serially connected, gating means coupled to the first and last stages of said shift register means for coupling said last stage to said first stage to form a closed loop, said gating means further having an input for receiving said train of signals, said gating means operative in response to said first clock pulses to open said loop from said last stage to said first stage, sample the bit in the train of signals serially coupled thereto, develop said binary signal corresponding to said sampled signal and couple same to said first shift register means first stage, said first shift register means being responsive to said first clock pulses to shift the contents of each stage in said shift register to the following stage and enter said sampled signal in said first stage, said clock means further coupling said third clock pulses to said shift register means, said shift register means being operative in response to said third clock pulses to shift said stored binary signals therethrough from output to input in one complete cycle.

8. The detector of claim 7 wherein said memory means includes storage register means for storing portions of each of said binary words corresponding to said predetermined binary words.

9. The detector of claim 7 wherein said memory means further includes, second shift register means, said storage register means being coupled to said second shift register means and said circuit means, and operative in response to said second mode select signal to couple one of said portions of a binary word to said second shift register means.

10. The detector of claim 9 wherein said predetermined binary words each include a predetermined number of information bits and a predetermined number of parity bits, said plurality of stages in said second shift register means being equal in number to said predetermined number of information bits, said second shift register means further including parity generation means coupled to said plurality of stages and operative in response to said information bits stored therein to develop said parity bits.

11. The detector of claim 10 wherein said second shift register means is coupled to said clock means and operative in responsive to said second clock pulses to shift said bits therethrough.

12. The detector of claim 11 wherein said clock means develops four first clock pulses during the interval of a bit time period and said clock means develops each of said second clock pulses on every fourth clock pulse.

13. The detector of claim 12 wherein said clock means further includes control circuit means operative to develop a first control pulse a predetermined period after each of said plurality of first clock pulses, and wherein said first gating circuit means is coupled to one of said stages of said first shift register means and one of said stages of said second shift register means, said counter means including fourth gating circuit means coupled to said first gating circuit means and counter register means coupled to said fourth gating circuit means, said fourth gating circuit means being operative in response to said first mode select signal to couple said comparison signals to said counter register means, said fourth gating circuit means being operative in response to said second mode select signal to inhibit coupling of said comparison signals to said counter register means and couple said first control pulses to said counter register means, said counter register means being operative to count a predetermined number of said first control pulses and develop said first timing signal, said fourth gating circuit means being operative in response to said reset mode select signal to inhibit coupling of said first control pulses to said counter register and couple said comparison signals thereto.

14. The detector of claim 13 wherein said fourth gating circuit means is further operative to couple said first control pulses to said counter register means when said fourth gating circuit means couples said comparison signals thereto, said counter-register means operative in response to said first control pulses to reset said counting signals indicative of a predetermined number of miscorrelations to a zero count.

15. The detector of claim 14 wherein said circuit means further includes first bistable means coupled to said counter register means and said fourth gating circuit means and operative in response to said comparison signals indicative of a predetermined number of miscorrelations to switch states terminating said first mode select signal and developing said second mode select signal, second bistable means coupled to said first bistable means, said counter register means and said fourth gating circuit means and operative in response to said second mode select signal and said first timing signal to develop said reset mode select signal, said timing means being coupled to said second bistable means to said clock means and operative in response to said reset mode select signal to develop said second timing signal, said timing means being operative in response to receipt of a predetermined number of said first control pulses to terminate said second timing signal.

16. The detector of claim 15 wherein said first bistable means includes means for developing an inverse second mode select signal in response to comparison signals indicative of a predetermined number of miscorrelations, said second gating circuit means being coupled to said first bistable means and operative in response to the presence of said comparison signals indicative of a predetermined number of miscorrelations, said inverse second mode select signal and said second timing signal to develop said detection signal.

17. The detector of claim 16 further including signal correlation means coupled to said sample and storage means and clock means, said signal correlation means being operative to compare the binary signals within each of a plurality of successive groups of said binary signals stored in a plurality of said stages of said sample and storage means and develop a second counting signal in response to a miscorrelation within each of said successive groups, and second circuit means coupled to said signal correlation means and operative in response to a predetermined number of said counting signals to inhibit coupling of said third clock signals from said clock means whereby said detector operation is terminated.

18. The detector of claim 17 wherein each of said successive groups of said binary signals includes a predetermined number of binary signals, said plurality of first clock pulses developed during the interval of one of said bit periods divided by the number of binary signals in one of said successive groups of said binary signals being an integer of at least two.

19. The detector of claim 18 wherein said signal correlation means includes fifth gating circuit means coupled to said sample and storage means and operative to compare the binary signals within said group of said binary signals in said stages and develop comparison signals in response to said miscorrelations, and second counter means coupled to said fifth gating means for counting said comparison signals, said second counter means developing said second counting signals in response thereto.

20. In a detector for detecting predetermined digital words within a train of signals wherein the digits in said words each have a predetermined time period and the detector samples each digit a plurality of times, circuitry for inhibiting the operation of said detector during the presence oF noise, or the like, in the train of signals including in combination;

timing means for developing a start signal at predetermined intervals, clock means being operative to develop a plurality of first clock pulses during the interval of a digit time period, circuit means coupled to said timing means and clock means and operative in response to said start signals to couple said first clock pulses from said clock means, sample and storage means, having a plurality of storage stages, coupled to receive said train of signals and further coupled to said circuit means for receiving said first clock pulses and responsive to each of said first clock pulses to sample the signals in the train of signals coupled thereto and store a digital signal corresponding to said sampled signal, signal correlation means coupled to said sample and storage means, said circuit means and said clock means, said signal correlation means being operative to compare to each other the digital signals within a predetermined group of said digital signals in said stages and develop counting signals in response to a predetermined number of comparisons of successive groups in said stages indicative of a predetermined number of miscorrelations, said circuit means being operative in response to a predetermined number of said counting signals to inhibit development of said first clock pulses whereby said detector operation is terminated.

21. In the detector of claim 20 wherein said plurality of first clock pulses developed during the interval of said digit time period divided by the number of digital signals within said group of said digital signals is an integer.

22. In the detector of claim 21 wherein each of said successive groups of said digital signals includes a predetermined number of digital signals, said plurality of first clock pulses during the interval of said digit time period divided by the number of digital signals in one of said successive groups of said digital signals being an integer of at least two.

23. In the detector of claim 22 wherein said signal correlation means includes first gating circuit means coupled to said sample and storage means and operative to compare the digital signals within said group of digital signals in said stages and develop comparison signals in response to the comparison therebetween, and counter means coupled to said first gating means for counting said comparison signals, said counter means developing said counting signals.

24. In the detector of claim 23 wherein said particular digital words each have a predetermined number of digits, said sample and storage means have a number of stages equal to said predetermined number of digits in one said words multiplied by said plurality of first clock pulses developed during the interval of said digit time period.

25. In the detector of claim 24 wherein said circuit means includes second gating circuit means coupled to said timing means and said clock means, said second gating circuit means operative in response to said start signal to allow said clock means to develop said first clock signals, and third gating circuit means coupled to said timing means and said counter means, said third gating circuit means being operative in response to said counting signals indicative of a predetermined number of miscorrelations to develop error signals, said second gating circuit means being coupled to said third gating circuit means and operative in response to said error signals coupled therefrom to inhibit development of said first clock pulses whereby said detector operation is terminated.

26. In the detector of claim 25 wherein said third gating circuit means includes bistable means coupled to said timing means and said second gating circuit means, said bistable means being operative in response to termination of said start signal and a timing signal from said second gating circuit means to change the number of miscorrelations necessary to develop said error signal.

27. In the detector of claim 26 further incLuding memory means for storing digital words corresponding to said predetermined digital words, comparison means coupled to said sample and storage means and said memory means and operative to compare said digital signals in said sample and storage means with a first digital word in said memory means, said comparison means being operative in response to a correlation between said digital signals and said first digital word to count a first period at least as long as the time period of said digital word and develop a first timing signal, said comparison means being further operative in response to said first timing signals to compare said digital signals in said sample and storage means with a second digital word in said memory means and develop a detection signal in response to a correlation therebetween.

28. In the detector of claim 27 wherein said first gating circuit means is coupled to a plurality of stages of said sample and storage means equal to the number of digital signals within said group of digital signals in said stages, said clock means being operative to develop a plurality of third clock pulses between said first clock pulses, and said counter circuit means count said comparison signals on particular ones of said third clock pulses.

29. In the detector of claim 28 wherein said plurality of first clock pulses during the interval of a digit period includes four clock pulses, said group of digital signals includes two digital signals, said first gating circuit means is coupled to the last and next to last stage of said sample and storage means and said counting means counts on every other third clock pulse.

30. In the detector of claim 29 wherein said second gating means is operative in response to two error signals in succession to inhibit coupling of said first clock signals from said first clock means.

31. A detector for detecting predetermined binary words within a train of signals wherein each bit in said word has a predetermined time period, said detector including in combination;

first timing means for developing a start signal having a first predetermined time period at predetermined intervals, clock means being operative to develop first clock pulses and third clock pulses, a plurality of said first clock pulses being developed during the interval of a bit time period, first circuit means coupled to said timing means and clock means for receiving said third clock pulses and operative in response to said start signals to couple said third clock pulses therefrom, sample and storage means, having a plurality of stages, coupled to said clock means and responsive to each of said first clock signals to sample the signals in the train of signals coupled thereto and store a binary signal corresponding to said sampled signal, signal correlation means coupled to said sample and storage means and clock means, said signal correlation means being operative in response to particular ones of said third clock pulses to compare to each other the binary signals within a group of said binary signals in said stages and develop first counting signals in response to a predetermined number of comparisons of successive groups in said stages indicative of a predetermined number of miscorrelations, said first circuit means being coupled to said signal correlation means and operative in response to a predetermined number of said counting signals to inhibit coupling of said third clock signals from said clock means whereby said detector operation is terminated, memory means for storing binary words corresponding to said predetermined binary words, comparison means coupled to said sample and storage means and said memory means and operative between said first clock pulses to compare said binary signals in said sample and storage means with a first binary word in said memory means, said comparison means being operative in response to a correlation between said binary signals in said sample and storage means and said first binary word to count a first time period at leasT as long as the time period of said binary word and develop a first timing signal, said comparison means being further operative in response to said first timing signal to compare the binary signals in said sample and storage means with a second binary word in said memory means and develop a detection signal in response to a correlation therebetween.

32. The detector of claim 31 wherein said predetermined binary words each include a plurality of binary bits and said sample and storage means includes a plurality of storage stages equal to the number of binary bits in one of said words multiplied by the plurality of first clock pulses developed during the interval of a bit time period.

33. The detector of claim 32 wherein each of said successive groups of said binary signals includes a predetermined number of binary signals, said plurality of first clock pulses during the interval of a bit time period divided by the number of binary signals in one of said successive groups of said binary signals being an integer of at least two.

34. The detector of claim 33 wherein said sample and storage means includes first shift register means having said plurality of stages serially connected, said signal correlation means including first gating circuit means coupled to a plurality of said stages of said sample and storage means and operative to compare the binary signals in said stages and develop comparison signals in response to the comparison therebetween, and first counter means coupled to said first gating circuit means for counting said comparison signals, said first counter means developing said first counting signals.

35. The detector of claim 34 wherein said comparison means includes second gating circuit means coupled to said sample and storage means and said memory means and operative to compare said binary signals in said sample and storage means with said first binary word in said memory means and develop comparison signals in response to a comparison therebetween, second counter means coupled to said second gating means for counting said comparison signals, said second counter means developing second counting signals in response to said comparison signals indicative of a predetermined number of miscorrelations, second circuit means operative in response to particular second counting signals to switch from a first mode select signal to a second mode select signal, said second counter means operative in response to said second mode select signal to inhibit counting of said comparison signals, to count for at least said first time period and develop said first timing signal, said memory means being operative in response to said second mode select signal to couple said second binary word to said comparison means, said second circuit means being operative in response to said first timing signal to develop a reset mode select signal, said second counter means operative in response to said reset mode select signal to count said comparison signals coupled thereto and develop counting signals indicative of a predetermined number of miscorrelations between said second binary word and said binary signals in said sample and storage means, said second circuit means operative in response to said particular counting signals to develop said detection signal.

36. The detector of claim 35 wherein said second circuit means further includes, timing means coupled to said second counter means and operative in response to said first timing signal to develop a second timing signal of predetermined period, and third gating circuit means coupled to said second counter means and timing means and being operative in response to said second timing signal and said second counting signals indicative of said predetermined number of said miscorrelations between said second binary word and binary signals to develop said detection signal.

37. The detector of claim 36 wherein said memory means includes, second shift register means and storage register means coupled to said second shift registEr means and said second circuit means, said storage register means storing portions of each of said binary words corresponding to said predetermined binary words, said storage register means being operative in response to said second mode select signal to couple one of said portions of a binary word to said second shift register means.

38. In a detector for detecting particular binary word sequences within a received train of signals wherein said words in said sequence each include a predetermined number of bits, each bit having a predetermined time period, the method including the steps of:

a. continuously sampling said received train of signals, a plurality of said sampling being taken within said time period of a bit, b. developing a binary signal corresponding to the sampled signal in said train of signals in response to each sampling, c. comparing a particular number of said binary signals to a stored binary word corresponding to the first word in said sequence, d. counting a first time period at least as long as the time period of a digital word in said sequence after a correlation between a predetermined number of particular binary signals and the bits of said stored binary word, e. comparing a second particular number of said binary signals to said second stored binary words corresponding to the second word in said sequence after termination of said first time period, and f. developing a detection signal in response to a predetermined number of correlations between said second particular number of said binary signals and the bits of said second stored binary word in said sequence.

39. The method of claim 38 wherein said particular number of binary signals compared to said stored binary words is equal to the predetermined number of bits in each of said words multiplied by the plurality of said samplings being taken within said time period of a bit.

40. The method of claim 39 wherein said plurality of said samplings being taken within the time period of said bit is four.

41. The method of claim 40 wherein said comparing of said binary signals to said stored binary words occurs between each of said samplings.

42. The method of claim 41 wherein four of said binary signals in said particular number of said binary signals are compared to one bit in said stored binary word.

43. The method of claim 42 wherein said train of signals is serially received and wherein said binary signals are stored in series.

44. In a detector for detecting the presence of a train of digital signals wherein the digits each have a predetermined time period, a method of inhibiting the operation of said detector in the presence of noise and the like, said method including the steps of:

a. continuously sampling said train of signals, a plurality of said samplings being taken within said time period of a digit, b. developing a digital signal corresponding to the sampled signal in said train of signals in response to each sampling, c. comparing a group of said digital signals occurring in sequence to one another and developing a comparison signal in response to a miscorrelation therebetween, d. counting said comparison signals developed in response to a number of comparisons in successive groups, and e. terminating the detecting operation in response to a predetermined number of said comparison signals being developed in a predetermined time period.

45. The method of claim 44 wherein said plurality of said samplings being taken within the time period of a digit divided by the number of digital signals within said group of digital signals in an integer.

46. The method of claim 45 wherein said integer is at least two.

47. The method of claim 46 wherein said plurality of said samplings being taken within the time period of said digit is four and the digital signals within a group is two.