UNIVERSAL DIGITAL DATA SYSTEM

• US 3,855,617 A
• Filed: 03/18/1974
• Issued: 12/17/1974
• Est. Priority Date: 08/29/1972
• Status: Expired due to Term

• Current Assignee: Gene S. Jankowski, Joseph A. Kibelbeck
• Original Assignee: Gene S. Jankowski, Joseph A. Kibelbeck
• Inventors: Jankowski, Gene S., Kibelbeck, Joseph A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Sachs, Michael C.
• Application Number:
  US05/451,922
• Time in Patent Office: 274 Days
• Field of Search: 360/32 179/15A,15BA,15BV,15BS
• US Class Current: 360/32
• CPC Class Codes: G11B 20/1419 to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Abstract

A system providing real-time acquisition of digital and analog data for transmission in a serial digital form to a remote data processor, for real-time playback, or for recording on an inexpensive magnetic recorder for later playback. The input data signals are applied to analog and digital multiplexers operating at variable sampling rates under control of a selectivelyvariable frequency clock and an A-to-D converter for providing a pulse train of parallel digital data to at least one parallelseries converter. The converter output comprises a train of serial digital data which may be directly transmitted to a data processor or to playback circuitry of the system, or which may be recorded. If the magnetic recorder is bandwidth limited, reduction of frequency range required by the serial digital data is accomplished by phase encoding. On direct playback or in playback from the recorder, the serial digital data is first phase decoded, if necessary, then converted back to parallel digital form. Provision is made to supply the parallel digital data to a data processor and a digital demultiplexer. The digital pulse train is also passed through a D-to-A converter and then demultiplexed to provide a plurality of analog outputs corresponding to the input analog signals. The playback circuitry is synchronized with the recording circuitry by means of clock pulses derived from the serial digital pulse train which are used in a phase-locked loop to control the frequency of the playback timing pulses.

Claims

1. A system for the acquisition recording and reproduction of digital and analog data derived from a plurality of digital and analog signal sources, comprising:

a. an analog multiplexer connected so as to sample said plurality of analog signals a predetermined number of times during a repetitive multiplexing cycle that defines a predetermined number of slots to provide a serial output signal comprising a train of analog samples lying in some, but not all of, said slots, said predetermined number of times being variable with respect to each of said plurality of analog signals so that at least one of said analog signals is sampled at a rate different than the rate said other analog signals are sampled;

b. an analog-to-digital converter, connected to said analog multiplexer so as to receive said serial output signal comprising a train of analog samples, for converting said analog samples into corresponding parallel format digital words to provide an output signal comprising a sequential train of parallel format digital words, one word being related to each of said analog samples, said sequential train of parallel format digitaL words having spaces therein determined by the slots of said repetive multiplexing cycle containing no related analog sample;

c. a digital multiplexer connected to sample said plurality of digital signals a predetermined number of times during said repetitive multiplexing cycle to provide parallel format digital words relating to said samples at times in said cycle corresponding to slots containing no analog sample, said predetermined number of times being variable with respect to each of said plurality of digital signals so that said digital signals may be sampled at different rates, said digital multiplexer also connected to receive said sequential train of parallel format digital words from said analog-to-digital converter and to insert said parallel format digital words related to said digital samples into spaces in said sequential train of parallel format digital words received from said analog-to-digital converter containing no related analog sample;

d. transmitter and parallel-to-series converter means connected to said digital multiplexer for converting said resultant sequential train of parallel format digital words into a predetermined number of pulse trains of serial digital words suitable for transmission and recording;

e. a first timing means connected for controlling said analog multiplexer, said analog-to-digital converter, said digital multiplexer and said transmitter and parallel to series converter means by inserting a sync signal into one slot defined by said repetitive multiplexing cycle said timing means also adapted to generate a series of encoding clock pulses having a known period;

f. a phase encoder connected to said transmitter and parallelto-series converter means and to said timing means so as to phase encode said pulse trains of serial digital words onto said series of encoding clock pulses having a known period;

g. a bandwidth limited magnetic tape transport having a plurality of recording channels at least equal in number to said predetermined number of pulse trains of serial digital words, said bandwidth limited magnetic tape transport being connected to said phase encoder for recording said phase encoded pulse trains of serial digital words on said plurality of channels on a one-to-one basis;

h. a phase decoder connected to said bandwidth limited magnetic tape transport so as to receive the phase encoded pulse trains of serial digital words recorded on the tracks of said bandwidth limited magnetic tape transport, said phase decoder including a transition detector which produces an output pulse for every transition in one of said pulse trains of phase encoded serial digital data words;

i. receiver and series-to-parallel converter means connected to the output of said phase decoder for converting said pulse trains of serial digital words into a sequential train of parallel format digital words;

j. a digital demultiplexer connected to the output of said receiver and series-to-parallel converter means for converting some of the words of said sequential train of parallel format digital words into digital signals equivalent to said sampled digital signals and some of the words of said sequential train of parallel format digital words into a set of parallel format digital words related to said sampled analog signals;

k. a digital-to-analog converter connected to said digital multiplexer to receive said set of parallel format digital words related to said sampled analog signals and convert said set of parallel format digital words into a serial train of analog signals equivalent to said sampled analog signal;

l. an analog demultiplexer connected to the output of said digital-to-analog converter for separating said serial train of analog signals into a plurality of analog signals related to said sampled analog signals; and

, m. a second timing means connected for receiving said sync signal and controlling said phase decoder, said receiver and series-to-parallel converter means, said digital Demultiplexer, said digital-to-analog converter and said analog demultiplexer by;

1. receiving the output pulses produced by said phase decoder for every transition in one of said pulse trains of serial digital data words and supplying encoding clock pulses back to the phase decoder by;

i. starting a clock enable pulse at a time slightly greater than one-half the known period or the encoding clock pulses after a given output pulse produced by said phase decoder for every transition in one of said pulse trains of serial digital data words occurs;

ii. terminating the clock enable pulse when the next subsequent output pulse, produced by said phase decoder for every transition in one of said pulse trains of serial digital data words, occurs;

iii. extracting encoding clock pulses from the output pulses, produced by said phase decoder for every transition in one of said pulse trains of serial digital data words upon the coincidence of a logic transition in said output pulses and said clock enable pulses; and

, iv. supplying the extracted encoding clock pulses back to said phase decoder; and

, 2. controlling the output frequency of a VCO by phase comparing the extracted encoding clock pulses with the output pulses generated by the VCO, the output of the VCO being used for controlling the operation of said digital demultiplexer, said digital-to-analog converter and said analog demultiplexer.

2. controlling the output frequency of a VCO by phase comparing the extracted encoding clock pulses with the output pulses generated by the VCO, the output of the VCO being used for controlling the operation of said digital demultiplexer, said digital-to-analog converter and said analog demultiplexer.

3. A system as claimed in claim 2 wherein said bandwidth limited magnetic tape transport means comprises a cassette-type audio tape recorder.

4. A system as claimed in claim 1 wherein said bandwidth limited magnetic tape transport means comprises a cassette-type audio tape recorder.