CLOCK SIGNAL ASSURANCE IN DIGITAL DATA COMMUNICATION SYSTEMS

• US 3,865,981 A
• Filed: 07/16/1973
• Issued: 02/11/1975
• Est. Priority Date: 07/16/1973
• Status: Expired due to Term

• Current Assignee: James P. Welch, Stephen R. Siegel
• Original Assignee: James P. Welch, Stephen R. Siegel
• Inventors: Welch, James P., Siegel, Stephen R.
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Krass, Errol A.
• Application Number:
  US05/379,304
• Time in Patent Office: 575 Days
• Field of Search: 178/69.5R,69.5DC 307/208,269 328/55,56,63,72 340/347DD,347AD
• US Class Current: 375/357
• CPC Class Codes: G11B 20/18 Error detection or correction; Testing , e.g. of drop-outs
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

In a digital data communication system of the type wherein digital data, synchronized by a reference clock, is applied to a counter, transitions of the digital data being utilized to reset the counter, the output of which is used to generate a coherant clock signal for the data, there is provided a system for assuring generation of the proper number of clock signals in the event of loss of data. According to the present invention, the counter is a recirculating counter and there is provided means responsive to the data for generating a data dropout signal when the amplitude level of the data falls below a predetermined threshold level and means responsive to the dropout signal for inhibiting the transitions of the data from resetting the counter which continues to circulate, permitting the output thereof to be decoded to generate artificial clock pulses during the duration of the dropout signal. The counter is clocked by timing pulses which are phase locked to the reference clock whereby the artificial clock pulses are related to the desired period of the data.

Claims

1. In a digital data communication system wherein digital data is utilized to generate a coherent clock signal for said data, the improvement comprising:

means responsive to said data for generating a data dropout signal when the amplitude level of said data falls below a predetermined threshold level;

means responsive to said dropout signal for inhibiting generation of said coherent clock signal; and

means responsive to said dropout signal for generating an artificial clock signal during the duration of said dropout signal.

2. In a digital data communication system according to claim 1, the improvement further comprising:

a recirculating counter, the output of said counter being used to generate said coherent clock signal, transitions of said digital data being utilized to reset said counter; and

wherein said inhibiting means is operative to inhibit said transitions of said data from resetting said counter.

3. In a digital data communication system according to claim 2, the improvement wherein the output of said counter is used to generate said artificial clock signal, said counter continuing to circulate, during the duration of said dropout signal.

4. In a digital data communication system according to claim 3 wherein said digital data is synchronized by a reference clock, the improvement further comprising:

a source of timing pulses, said timing pulses being applied to said recirculating counter for clocking the same; and

means for phase locking said timing pulses to said reference clock whereby said artificial clock signal is related to the desired period of said data.

5. In a digital data communication system according to claim 3, wherein said digital data is synchronized by a reference clock, the improvement wherein said recirculating counter is driven by timing pulses, the frequency of which is a fixed multiple of the frequency of said reference clock.

6. In a digital data communication system according to claim 3, the improvement further comprising:

means responsive to termination of said dropout signal for delaying application of said data transitions to said recirculating counter for at least one bit period of said digital data.

7. In a digital data communication system according to claim 1, the improvement wherein said inhibiting means is responsive to termination of said dropout signal for permitting generation of said coherent clock signal, and further comprising:

means responsive to termination of said dropout signal for delaying generation of said coherent clock signal for a time sufficient to allow spurious transitions of said data to be avoided.

8. In a digital data communication system according to claim 7, the improvement wherein said delay is at least one bit period of said digital data.

9. In a digital data communication system according to claim 1, the improvement further comprising:

delay means interposed in the path of said digital data, said delay being approximately one-quarter of the period of the highest frequency of said digital data, said delay means being interposed between said digital data and said inhibiting means.

10. In a digital data communication system according to claim 1, the improvement wherein said data dropout signal generating means comprises:

a comparator having positive and negative reference levels, said comparator being responsive to said data for generating said data dropout signal whenever the amplitude level of said data lies between said positive and negative reference levels.

11. In a digital data communication system wherein digital data, synchronized by a reference clock, is applied to a counter, transitions of said digital data being utilized to reset said counter, selected counts from said counter being used to generate a coherent clock signal for said data, the improvement wherein said counter is a recirculating counter and comprising:

means responsive to said data for generating a data dropout signal when the amplitude level of said data falls below a predetermined threshold level; and

means responsive to said dropout signal for inhibiting said transitions of said data from resetting said counter whereby said counter continues to circulate, the counts from which are used to generate an artificial clock signal during the duration of said dropout signal.

12. In a digital data communication system according to claim 11, the improvement further comprising:

delay means interposed in the path between said digital data and said inhibiting means, said delay means delaying said data by approximately one-quarter of the period of the highest frequency of said data.

13. In a digital data communication system according to claim 12, the improvement wherein said data dropout signal generating means is also responsive to an output of said counter.

14. In a digital data communication system according to claim 12, the improvement wherein said data dropout signal generating means is also responsive to the delayed digital data from said delay means.

15. In a digital data communication system according to claim 11, the improvement wherein said inhibiting means is responsive to termination of said dropout signal for permitting said transitions of said data from resetting said counter, and further comprising:

means responsive to termination of said dropout signal for inhibiting said transitions of said data from resetting said counter for a time sufficient to allow spurious transitions of said data to be avoided.

16. In a digital data communication system according to claim 15 wherein said time is at least one bit period of said digital data.

17. In a digital data communication system according to claim 11, the improvement further comprising:

a source of timing pulses, said timing pulses being applied to said recirculating counter for clocking the same; and

means for phase locking said timing pulses to said reference clock whereby said artificial clock signal is related to the desired period of said data.

18. In a digital data communication system according to claim 17, the improvement wherein the frequency of said timing pulses is a fixed multiple of the frequency of said reference clock.

19. In a digital data communication system according to claim 11, the improvement wherein said data dropout signal generating means comprises:

a comparator having positive and negative reference levels, said digital data being applied to said comparator, said comparator generating said data dropout signal whenever the amplitude level of said data lies between said positive and negative reference levels.

20. A digital data communication system responsive to input data, in analog form, synchronized by a reference clock comprising:

delay means responsive to said data for delaying said data by approximately one-quarter of the period of the highest frequency of said data;

detector means responsive to the output of said delay means for generating a pulse for each leading and trailing edge transition of said delayed data;

a recirculating counter having a reset input and a timing pulse input;

first gate means interposed between the output of said detector means and said reset input of said counter, said transition pulses being utilized to reset said counter;

means responsive to said data reference clock for generating a plurality of coherent timing pulses, said timing pulses being applied to said timing pulse input of said counter for clocking the same;

means responsive to at least one selected count output of said counter for generating a coherent clock signal for said data; and

means responsive to said data for generating a data dropout signal when the amplitude level of said data falls below a predetermined reference level, said data dropout signal being applied to said first gate means for inhibiting said transitions of said data from resetting said counter, whereby said counter continues to circulate, under the control of said timing pulses, at least one selected count output of said counter being used to generate an artificial clock signal during the duration of said dropout signal.

21. A digital data communication system according to claim 20 further comprising:

second gate means interposed between said input data and said delay means; and

dropout detector means responsive to said data dropout signal for generating a first inhibiting signal, said first inhibiting signal being applied to said first and second gate means, said second gate means inhibiting said data from being applied to said delay means.

22. A digital data communication system according to claim 21 wherein said data dropout signal generating means is responsive to the amplitude level of said data rising above said predetermined reference level for terminating said data dropout signal, said dropout detector means being responsive to termination of said dropout signal for removing said first inhibiting signal from said first and second gate means, and further comprising:

means responsive to termination of said first inhibiting signal for generating a second inhibiting signal, said second inhibiting signal having a time period sufficient to allow spurious transitions of said data to be avoided, said second inhibiting signal being applied to said first gate means for inhibiting said transitions of said data from resetting said counter for said time period.

23. A digital data communication system according to claim 22 wherein said second inhibiting signal generating means is further responsive to at least one selected count output of said counter, said second inhibiting signal generating means utilizing said selected count output of said counter for establishing said time period.

24. A digital data communication system according to claim 21 wherein said dropout detector means is also responsive to at least one selected count output of said counter.

25. A digital data communication system according to claim 21 wherein said dropout detector means is also responsive to said output of said transition detector means.

26. A digital data communication system according to claim 20 wherein said input data is phase-encoded in accordance with a bi-phase format and wherein said selected count output of said counter which is utilized for generating both said coherent clock signal and said artificial clock signal represents more than one-half of a bit period but less than one full bit period of said data.

27. A digital data communication system according to claim 26 wherein said selected count represents three-quarters of a bit period of said data.

28. A digital data communication system according to claim 26 further comprising:

means responsive to the output of said first gate means and said selected count output of said counter for generating and applying to said first gate means an inhibiting pulse for inhibiting selected transition pulses from passing through said firsr gate means, said inhibiting pulSe beginning when a transition passes through said first gate means and ending upon the occurrence of the next selected count output of said counter.

29. A digital data communication system according to claim 20 wherein said input data is phase-encoded in accordance with a double density format and wherein said coherent clock signal generating means is responsive to three selected count outputs of said counter and to said transition pulses.

30. A digital data communication system according to claim 29 further comprising:

means responsive to four selected count outputs of said counter during said dropout signal for generating said artificial clock signal, at least some of said selected count outputs being different from the selected count outputs utilized by said coherent clock signal generating means whereby the phase of said artificial clock signal is shifted by one-quarter of a bit period from the phase of said coherent clock signal.

31. A digital data communication system according to claim 20 wherein said input data is phase-encoded in accordance with a bi-phase format and wherein said delay means delays said data by one-quarter of a bit period of said data.

32. A digital data communication system according to claim 20 wherein said input data is phase-encoded in accordance with a double density format and wherein said delay means delays said data by one-half of a bit period of said data.