METHOD AND APPARATUS FOR MAINTAINING THE CHARGE ON A STORAGE NODE OF A MOS CIRCUIT

• US 3,870,901 A
• Filed: 12/10/1973
• Issued: 03/11/1975
• Est. Priority Date: 12/10/1973
• Status: Expired due to Term

• Current Assignee: Kent F. Smith, Robert J. Huber
• Original Assignee: Kent F. Smith, Robert J. Huber
• Inventors: Smith, Kent F., Huber, Robert J.
• Primary Examiner(s): Lynch, Michael J.
• Assistant Examiner(s): Anagnos, L. N.
• Application Number:
  US05/423,422
• Time in Patent Office: 456 Days
• Field of Search: 307/205,214,238,279,304 340/173AM,173FF
• US Class Current: 365/228
• CPC Class Codes: G11C 11/4023 using field effect transistors
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: H03K 17/24 Storing the actual state when the supply voltage fails
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356052 using pass gates
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

Method and apparatus for maintaining the charge on a storage node of a MOS circuit of the type having a depletion mode transistor as a load resistor situated between a voltage source and a storage node. The voltage level of the storage node determines the output of the circuit. The storage node is charged to a first voltage level upon the receipt of a given data input to the circuit. The substrate of the circuit is reversed biased to a level sufficient to render the depletion mode transistor nonconducting. This will isolate the storage node and isolation will continue for a time selected to maintain a residual charge of a given magnitude on the storage node if the node was originally charged. The substrate bias is removed to permit the depletion mode transistor to again become conductive. If the residual charge was present on the storage node, the node is permitted to recharge thus returning the node to the first voltage level and re-establishing the output of the circuit. In this way power consumption is minimized while the state of the circuit is maintained.

Claims

1. Method for maintaining the charge on a storage node of a MOS circuit of the type having a depletion mode transistor as a load resistor situated between a voltage source and the storage node comprising the steps of permitting the storage node to charge to a given voltage upon receipt of a given input signal to the circuit from an internal storage node, reverse biasing the substrate of said transistor to isolate the storage node, permitting the charge on the storage node to decay if the storage node was originally charged and removing the bias on the substrate while some residual charge still remains on said storage node to permit recharging of the storage node if the input signal is still present.

2. The method of claim 1 wherein the step of reverse biasing the substrate does not take place until after a time sufficient for the storage node to charge to the level of the voltage source.

3. The method of claim 1 wherein the step of removing the reverse bias from the substrate is initiated prior to the end of the storage node decay time.

4. A method of maintaining the charge on a storage node of a MOS circuit whose input is connected to an internal storage node, said circuit being of the type having first and second inverter circuits connected in series each of which utilizes a depletion mode transistor as a load device situated between a voltage source and the storage node thereof, the method comprising the steps of charging the storage node of the first inverter to a given voltage level if a data input of a given polarity is present, reverse biasing the substrate to isolate the storage nodes respectively, permitting the charge on the storage node of the first inverter to decay if same was originally charged, and removing the reverse bias to render the depletion mode transistors conductive while some residual charge still remains on said storage node and thereby effective to recharge the storage node of the first inverter if the input signal is still present, said residual charge being effective to prevent charging of the storage node of the second inverter.

5. The method of claim 4 wherein the step of reverse biasing the substrate does not take place until after a time sufficient for the storage node to charge to the level of the voltage source.

6. The method of claim 4 wherein the step of removing the reverse bias from the substrate is initiated prior to the end of the storage node decay time.

7. A method for maintaining the charge on a storage node of a MOS circuit of the type having a pair of cross-coupled inverter subcircuits each of which has a storage node connected between a depletion mode load transistor and a driver transistor, each inverter subcircuit being connected between a voltage source and ground and having the control terminal of its driver transistor connected to the storage node of the other inverter, the method comprising the steps of charging one of the storage nodes in accordance with the input of the circuit, reverse biasing the substrate of the transistors to isolate the storage nodes respectively, maintaining a residual charge on the charged storage node, and removing the reverse bias from the substrate to render the depletion mode transistors conductive and to cause the storage node with residual charge thereon to render conductive the driver transistors whose control terminal is connected therEto thereby preventing the other storage node from recharging, and thus returning the circuit to its original logic state.

8. The method of claim 7 wherein the step of reverse biasing the substrate does not take place until after a time sufficient for the storage node to charge to the level of the voltage source.

9. The method of claim 7 wherein the step of maintaining the residual charge on the storage node comprises initiating the step of removing said reverse bias from the substrate prior to the end of the storage node decay time.

10. A method for reducing the refreshing power requirements of a random access memory during power failure of a primary power source wherein the memory utilizes depletion mode transistors as load resistors in a flip-flop circuit between the respective storage nodes thereof and a voltage source comprising the steps of charging one of the storage nodes in accordance with the input of the memory, sensing the occurrence of a power failure in said primary power source, and, in response thereto, (a) connecting an auxiliary power source to said memory and (b) reverse biasing the substrates of the depletion mode transistors to isolate the respective storage nodes, maintaining a residual charge on the charged storage node and removing said reverse bias from the substrates of the depletion mode transistors to render same conductive to connect the storage nodes to the auxiliary power source thus causing the storage node with the residual charge thereon to actuate the circuit to permit only the residually charged storage node to recharge, and if necessary repeating the application and removal of said reverse bias for as long as the failure of said primary power source continues.

11. The method of claim 10 wherein the steps of applying and removing said reverse bias are performed by generating a series of pulsed signals to the transistor substrate.

12. The method of claim 11 wherein the voltage on said storage node will decay to an inoperative level within a given period of time, the width of said pulse signals being less than said given period of time, whereby a residual charge is maintained on said storage node.

13. The method of claim 12 wherein the voltage on said storage node will charge to an operative level in a given period of time, the time between pulses in said pulsed signal being at least as long as said given period of time.

14. The method of claim 11 wherein the voltage on said storage node will charge to an operative level in a given period of time, the time between pulses in said pulsed signal being at least as long as said given period of time.

15. Circuitry for maintaining the charge on a storage node of a MOS circuit of the type utilizing a depletion mode transistor as a load resitor situated between a voltage source and a storage node comprising means operably connected to the input node of the circuit to effect charging of the storage node by the voltage source upon receipt of a given input signal, means for reverse biasing the substrate of the transistor to isolate the storage node, means for maintaining a residual charge on the storage node if the storage node was originally charged and means for removing the reverse bias from the substrate of the transistor to render the transistor conductive such that the storage node is permitted to recharge if residual charge is present thereon.

16. The circuitry of claim 15 wherein said means for reverse biasing and means for removing the reverse bias comprise a pulse generator operably connected to the substrate of the depletion mode transistor and generating a pulsed signal comprising a series of pulses of predetermined width.

17. Apparatus for maintaining the charge on a storage node of a MOS circuit of the type having a pair of inverters each of which has a depletion mode transistor as a load resistor situated between a voltage source and a storage node and a driver transistor whose output circuit is connected between the storage node and ground, the control tErminal of the driver of the first inverter being connected to the circuit input, the control terminal of the driver of the second inverter being connected to the storage node of the first inverter and the storage node of the second inverter being connected to the circuit output, the storage node of said first inverter being charged by said voltage source if an input signal of a given polarity is received by the circuit, said apparatus comprising means for reverse biasing the substrate of the transistors to isolate said storage nodes respectively, means for maintaining a residual charge of a given magnitude on the storage node of said first inverter if same was originally charged, means for removing said bias to render said load transistors conductive and if residual charge was present on the storage node of said first inverter to render the driver transistor of the second inverter conductive thereby preventing the storage node of said second inverter from charging.

18. The apparatus of claim 17 wherein said given magnitude is at least equal to the threshold voltage of the driver of said second inverter.

19. The apparatus of claim 17 wherein the voltage on said storage node will charge to an operative level in a given period of time, the time between pulses in said pulsed signal being at least as long as said given period of time.

20. A random access memory utilizing a flip-flop circuit having reduced power requirements during failure of the primary power source of the type using depletion mode transistors as load resistors connected to the respective storage nodes in the flip-flop circuit, said memory comprising an auxiliary voltage source capable of being connected to the input of the depletion mode transistors to permit charging by said auxiliary voltage source of one of the respective storage nodes to a higher level than the other in accordance with the input of the memory, means for sensing the occurrence of a power failure in the primary power source, means for connecting said auxiliary power source to said memory when a power failure is sensed, means for reverse biasing the substrates of the depletion mode transistors to isolate the respective storage nodes, means for maintaining a residual charge on the storage node charged to a higher level and means for removing said reverse bias from the substrates of the depletion mode transistors to render same conductive such that the storage node having the residual charge thereon is effective to actuate the circuit to prevent charging of the other storage node.

21. The memory of claim 20 wherein the voltage on said storage node will decay to an inoperative level within a given period of time, and wherein said maintaining means comprises timing means for actuating said reverse bias removal means after a time less than said given time period.

22. The memory of claim 21 wherein said substrate reverse biasing means, said substrate bias removal means and said timing means comprise a pulse generator operably connected to the substrate of the depletion mode transistors, said pulse generator generating a pulsed signal comprising a series of pulses of predetermined width.

23. The memory of claim 22 wherein said pulse width is less than the time period necessary for said storage node to decay to an inoperative level.

24. The memory of claim 22 wherein the interval between pulses is at least equal to the time necessary for said storage node to charge to an operative level.

25. The memory of claim 24 wherein said operative level is the auxiliary voltage source voltage.

26. The memory of claim 20 wherein the voltage on said storage node will charge to an operative level within a given period of time, and wherein said substrate reverse biasing means is not actuated until after said given time period.