IN CIRCUIT ELECTRONIC COMPONENT TESTER

• US 3,870,953 A
• Filed: 08/01/1972
• Issued: 03/11/1975
• Est. Priority Date: 08/01/1972
• Status: Expired due to Term

• Current Assignee: Schlumberger Systems & Services Incorporated
• Original Assignee: Melvin R. Hall, Roger M. Boatman
• Inventors: Boatman, Roger M., Hall, Melvin R.
• Primary Examiner(s): Corcoran, Robert J.
• Application Number:
  US05/277,085
• Time in Patent Office: 952 Days
• Field of Search: 324/73R,73PC,73AT,158R,158T
• US Class Current: 324/72.5
• CPC Class Codes: G01R 31/31915 In-circuit Testers

Abstract

Test apparatus which is adapted to test circuit components while connected to a printed circuit board. The described apparatus is capable of functionally testing dual in-line, sixteen-terminal, integrated circuit components and to supply all of the power necessary for exercising the IC while the printed circuit board is removed from the equipment. Selected terminals of the IC package are provided with operating power level voltages, other terminals are applied with signal voltages, and the voltages on other terminals are compared with predicted voltages. The signal voltages are driven with sufficient power to force the IC through its expected mode of operation, and the duration of the test interval is maintained sufficiently small, on the order of less than 10 Mu seconds and normally less than 1 Mu second to avoid damage to other components on the circuit board.

Claims

1. Electrical circuit test apparatus for use with a support base having electrical conductors and a plurality of housings mounted on said support base, each of said housings having a plurality of electrical terminals which serve as electrodes for active circuits contained in said housings with the electrical terminals on one housing being directly connected to electrical terminals on the other housings for transmitting electrical signals therebetween;

said apparatus being characterized by having a connector member comprising a plurality of electrical terminals adapted to simultaneously engage the electrical terminals on one of said housings while said housing is on said support base with its terminals connected to said electrical conductors, said member being adapted to be selectively placed on different ones of said housings one at a time in seriatim to thereby test the circuits in the housings individually; and

circuit means connected to the individual terminals of said connector member for supplying a signal voltage having an amplitude sufficient to test proper operation of an active circuit during a period of less than about 10 Mu seconds to be sufficiently short to prevent damage to electrical components not being tested by said signal voltage that are in housings connected to said support base and for producing an indication of the operation of the tested circuit, said indication lasting beyond the end of the test period.

2. Apparatus of claim 1 wherein the circuit means includes a first current driver circuit for supplying a power level voltage to a first pair of terminals on said component housing;

a second current driver circuit for supplying said signal voltage to a component housing terminal not in said first pair; and

a timing circuit for initiating said signal voltage of limited duration after the power level voltage has been initiated.

3. Apparatus of claim 2 wherein the circuit means for producing an indication of the operation of the tested circuit comprises means responsive to a change in the current conductivity of said active circuit under test during the testing period for producing a visual manifestation thereof which persists after the test period has concluded.

4. Apparatus of claim 3 wherein said means responsive to a change in current conductivity includes a counting circuit and the visual manifestation is provided by a digit display device connected to the counting circuit.

5. Apparatus of claim 3 wherein each housing has a plurality of acTive circuits and the circuit means of said test apparatus comprises for each active circuit first and second current driver circuits for supplying power level voltages and for supplying signal voltages;

and a timing circuit connected to said driver circuits for simultaneously testing all of the circuits in a housing.

6. Apparatus of claim 1 wherein the circuit means for producing an indication of the operation of the tested circuit includes means responsive to a change in the current conductivity of the active circuit under test during the test period for producing a visual manifestation which persists after the test period has concluded.

7. Apparatus of claim 1 wherein the housings contain integrated circuits and said circuit means comprises a pair of current driver means for selectively supplying predetermined voltages to each of said terminals;

program means for controlling each of said current driver means to selectively supply power or signal voltage or to inhibit said current driver means; and

timing circuits connected to each current driver means for providing power voltages where programmed to be supplied to the various connector member pins, said timing circuits also serving to limit the duration of the signal voltages to provide a test period of less than about 10 Mu seconds.

8. Apparatus of claim 7 wherein the circuit means for producing an indication of the operation of the tested circuits includes a predict register for each connector member terminal and connected to be controlled by said program means;

a result register connected to each connector member terminal; and

a circuit controlled by said timing circuits for comparing the contents of the predict and result registers at the end of said test period.

9. Apparatus of claim 1 whrein said circuit means for producing an indication of the operation of the tested circuit includes a predict register connected to be controlled by an operator;

a result register connected to a terminal of the circuit under test; and

indicating means connected to be responsive to a comparison in the predict and result registers.

10. Apparatus as defined in claim 1 wherein the signal voltage comprises a plurality sequential pulses with each pulse being applied to a different housing terminal and the indication is initiated only during the duration of the last of said plurality of pulses.

11. Apparatus as defined in claim 1 wherein the signal voltage comprises a plurality of simultaneously generated pulses each of which are applied to a different housing terminal.

12. Apparatus as defined in claim 11 wherein the simultaneously generated pulses have opposite polarities.

13. Apparatus for testing logic circuits packaged in housings having dual rows of in-line terminals while said housings are in circuit on a printed circuit board comprising a connector member having dual rows of in-line pins and being adapted for connection to the terminals of one of said housings;

circuit means connected to the individual pins of the connector member for supplying voltages to test the proper operation of the logic circuits in a housing, said circuit means including timing circuits for applying said voltages for a test period that is sufficiently short to prevent damage to logic circuits in other housings on said circuit board; and

means for producing an indication of the operation of the tested circuits at the end of the test period, said indication lasting beyond the end of the test period.

14. Apparatus of claim 13 wherein said circuit means further includes:

current driver means for selectively supplying predetermined voltages to each of said pins and program means for controlling each of said current driver means to selectively supply power or signal voltages or to inhibit said current driver means; and

wherein the timing circuits are connected to each current driver means for providing power voltages where programmed to be supplied to the various connector member pins, said timing circuits also limIting the duration of the signal voltages to less than about 10 Mu seconds.

15. Apparatus of claim 14 wherein said indicating means comprises a predict register for each connector member pin and connected to be controlled by said program means, a result register connected to each connector member pin, and a further circuit means controlled by said timing circuits for comparing the contents of the predict and result registers at the end of the application of said signal voltages.

16. Apparatus of claim 13 wherein said circuit means further includes a program means and current driver means for selectively supplying predetermined voltages to a plurality of said pins in response to operation of said program means;

and wherein said timing circuits include gating signal generators which produce during each test cycle a first signal to control generation of power level voltages by said current driver means, a second signal to control generation of signal voltages by said current driver means, and a third signal to terminate the test cycle sufficiently soon after the generation of the second signal to prevent damage to logic circuits in other housings on said circuit board.

17. Apparatus of claim 16 wherein the timing circuits which generate said second signal include a counting circuit for producing a plurality of pulses, and circuit connections between said program means and said timing circuits whereby the number of pulses produced in said second signal is determined by said program means.

18. Apparatus of claim 17 wherein the timing circuits which generate said second signal include means for generating a preliminary signal which occurs ahead of the first of said plurality of pulses whereby during the testing of a counter circuit, said preliminary signal is used to set a predetermined count in said counter before said plurality of pulses are produced.

19. Apparatus of claim 17 wherein said indicating means includes a transition detector adapted to be connected to a connector member pin, a counter circuit connected to the output of said transition detector, and means for indicating the number of transitions on said connector member pin during said test cycle.

20. A method for individually testing integrated circuit packages in seriatim while mounted on a circuit board and in circuit by test apparatus having a multipin connector member adapted to be engaged with and be removed from terminals on each package as the package is tested, said method comprising:

a. applying said connector member to terminals of a first package to be tested with different pins engaging different ones of said terminals while the integrated circuit package remains electrically connected in the circuit;

b. testing each circuit package during one or more test cycles with each test cycle including the steps of;

i. applying an operating power voltage level across selected ones of said connector pins;

ii. thereafter applying one or more signal voltages to other connector pins for causing said circuit, if operating properly, to assume a predicted mode of operation, said signal voltage being applied for a duration of time sufficiently short to prevent damage to other circuit packages connected in the circuit but not under test;

iii. comparing the actual mode of operation assumed by the circuit under test with a predicted mode of operation;

c. thereafter removing said connector member from said first circuit package to a second circuit package on the same circuit board; and

d. testing the second package by repeating steps (i), (ii), and (iii) recited above.

21. The method of claim 20 further including the step of providing in the test apparatus for each terminal of said package a separate program selector, a separate current driver and a separate register, and wherein the test cycle includes also the steps of controlling the current drivers by adjusting the program selector, and comparing the signal in the register with a predicted signal to iNdicate the proper operation of the package under test.

22. The method of claim 21 further including the step of providing in the test apparatus a timing circuit, and wherein the test cycle includes also controlling the current drivers by signals received from said timing circuit to thereby effect the applying of the operating power voltage levels at a first time during each test cycle and the applying of the signal voltages at a subsequent time during each test cycle;

and at the end of said test cycle removing said voltage levels and signal voltages substantially simultaneously after the registers have assumed a condition resulting from the test cycle.

23. A method of testing IC units while the IC units are electrically connected in a digital circuit arrangement comprising:

simultaneously accessing all the terminals of an IC unit to be tested;

initiating a test cycle which includes supplying signal voltages on selected input terminals with sufficient drive to force the IC circuit to function in a predetermined manner, said voltages being applied for a time period sufficiently short to prevent damage to other IC units in the circuit arrangement; and

monitoring the voltage level on the terminals of the IC unit under test by storing the voltage levels on the terminals at the end of the test cycle and comparing the stored voltage levels with predicted voltage levels.

24. The method of claim 23 further including the steps of:

providing a predict register for each terminal of the IC unit to be tested;

providing a storage register that is connected to each terminal of the IC unit under test; and

adjustably controlling a programming member to provide all of the voltage levels for each of the predict registers.

25. The method of claim 24 further including the step of adjustably controlling the programming member to control the polarity and timing of voltages that are supplied to said selected input terminals.

26. The method of claim 24 wherein the test cycle includes the steps of:

generating logical one and zero power voltage levels which are applied to predetermined terminals of the IC unit under test;

then after a stable conduction condition has been established in the IC unit under test, generating said signal voltages for a period of not longer than about 10 seconds; and

at the end of said test cycle, generating a signal which causes the voltage levels on the terminals of the IC unit under test to be stored and compared with the voltage levels in the predict register.

27. The method of claim 26 wherein the IC unit is a binary counting circuit, and the step of supplying signal voltages includes the steps of clearing said counting circuit with a first signal, then entering a predetermined count into said counting circuit with a second signal, and thereafter adding a predetermined number of counts to the count in said counting circuit with a third signal.

28. A method for testing electronic circuit components while connected in an electrical circuit and mounted on a circuit board without damage to associated components on the same circuit board comprising the steps of:

accessing the individual terminals of the component to be tested;

applying operating voltage levels to selected ones of said terminals of the component under test for a first time period;

after the start of and during said time period when the resultant voltages in the circuit have stabilized subsequently applying during a brief second time period a signal voltage to a terminal of said component under test, said operating voltage and signal voltage having an amplitude and duration (i) sufficient to cause the tested component to attain temporarily a predicted conducting condition but (ii) insufficient to cause damage to said associated components connected in the same circuit; and

producing an indication in response to operation of said tested component at the end of said time period, said indication lasting sIgnificantly beyond the end of the period during which said operating and signal voltage are applied.

29. The method of claim 28 wherein the components are packaged in housings having multiple terminals soldered to a printed circuit member and wherein said operative voltage levels and signal voltages are applied to selected housing terminals by:

providing a separate control circuit for each housing terminal;

adjusting each control circuit to selectively provide a voltage level, a signal voltage, or no voltage; and

actuating a timing circuit which causes the control circuits to apply to the housing terminals first the voltage levels, then the signal voltages and thereafter actuates circuit arrangements for producing the indication of operation of the circuits in the housing tested.

30. The method of claim 29 wherein voltage levels are applied to said housing terminals by providing a separate current driver circuit for each terminal including two normally non-conducting transistors connected in series across positive and negative poles of a power supply, and actuating one or the other but not both of said transistors to selectively apply to the various housing terminals either a logical one or zero voltage level.

31. The method of claim 29 wherein the signal voltages are applied to said housing terminals by providing a separate current driver circuit for each terminal including two normally non-conducting transistors connected in series across positive and negative poles of a power supply, and actuating one or the other but not both of said transistors to selectively apply to the various housing terminals either a logical one or zero signal voltage.

32. The method of claim 29 wherein voltage levels are applied to said housing terminals by providing a pair of separate current driver circuits for each terminal and actuating either one driver circuit to supply said voltage levels or the other driver circuit to supply said signal voltage.

33. The method of claim 32 wherein said current driver circuits are selected in response to the adjustment of the associated control circuit, and the actuation of the selected current driver circuit for each terminal is controlled by gating signals generated from a timing circuit.

34. The method of claim 33 wherein each current driver circuit comprises two normally non-conducting transistors connected in series across positive and negative poles of a power supply with the connection to the housing terminal being at a common junction between said transistors, and the selected voltage level or signal voltage for each terminal is provided by causing only one of the four transistors connected to such terminal to be conductive during a test cycle.

35. Apparatus for in-circuit testing of transistors, said apparatus having terminals adapted for connection to the emitter, collector and base terminals of the transistor under test and comprising:

a source of direct current voltage, current driver circuits capable of providing either of two polarities of voltage, connected to said voltage source and to each of said apparatus terminals;

timing and logic circuits connected to control said current driver circuits and effective with each transistor being tested to cyclically produce in cooperation with said voltage source;

i. during a first time period a voltage difference of a first polarity between the terminals adapted to be connected across the emitter and collector terminals, ii. during a second time period a voltage difference of opposite polarity between the same terminals, iii. during each of said time periods a voltage pulse having an amplitude, polarity and duration sufficient to cause a current flow in the emitter-collector circuit of a properly operating transistor under test during only one of said time periods but insufficient to cause damage to any other electrical circuit components connected in-circuit with said transistor; and

a display device including a currEnt transistion detector to detect a presence or absence of a current flow in the emitter-collector circuit for indicating a faulty transistor.

36. Apparatus as defined in claim 35 wherein the display device includes a first visual signal for identifying an operative P-N-P transistor, a second visual signal for identifying an operative N-P-N transistor, anad a third visual signal for identifying a faulty transistor.

37. A method for in-circuit testing of transistors while electrically connected to electrical conductors on a support base and to other circuit components that are unpowered except for voltages applied during a test period, said method being characterized by:

providing a probe having a plurality of electrical terminals adapted to simultaneously engage all the electrical terminals on the transistor under test while the transistor is on said support base with its terminals connected to said electrical conductors;

applying an operating direct voltage level of a first polarity to the collector and emitter terminals of said transistor under test for a first time period;

during said first time period, applying a first signal voltage to the control terminal of said transistor under test, the start of said first signal voltage being delayed for a period sufficient to allow the previously applied voltage level to reach a steady condition, said first signal voltage having an amplitude and duration i. sufficient to cause the tested transistor to attain temporarily a predicted conducting condition if the transistor is not faulty and the polarity of the operating voltage level is proper, but ii. insufficient to cause damage to said associated components connected in the same circuit;

producing an indication in response to proper operation of said tested transistor at the end of said time period, said indication lasting significantly beyond the end of the period during which said signal voltage is applied;

thereafter applying an operating direct voltage level of reversed polarity to the collector and emitter terminals of said transistor under test for another time period;

during said other time period, applying a second signal voltage to the control terminal and said transistor under test, the start of said second signal voltage being delayed for a period sufficient to allow the previously applied voltage level to reach a steady condition, said second signal voltage having an amplitude and duration i. sufficient to cause the tested transistor to attain temporarily a predicted conducting condition if the transistor is not faulty and the polarity of the operating voltage level is proper, but ii. insufficient to cause damage to said associated components connected in the same circuit; and

producing an indication in response to proper operation of said tested transistor at the end of said other time period, said indication lasting significantly beyond the end of the period during which said signal voltage is applied.