FLIP CHIP MODULE WITH NON-UNIFORM CONNECTOR JOINTS

• US 3,871,015 A
• Filed: 08/14/1969
• Issued: 03/11/1975
• Est. Priority Date: 08/14/1969
• Status: Expired due to Term

• Current Assignee: Edwin M. Winter, Paul T.C. Lin
• Original Assignee: Edwin M. Winter, Paul T.C. Lin
• Inventors: Lin, Paul T. C., Winter, Edwin M.
• Primary Examiner(s): James, Andrew J.
• Application Number:
  US04/850,094
• Time in Patent Office: 2,035 Days
• Field of Search: 317/234,235,5,5.2,5.3,5.4,11A,11CC 29/576,589,588,587,590,591,626 174/52,52.3
• US Class Current: 257/779
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

The interconnecting joints between a semiconductor chip and a substrate are not uniform, but differ in shape or material. The difference results in different abilities to withstand shear stress and increases the device lifetime. A volume differential causes a stress resistance differential in the interconnection joints.

Claims

1. A semiconductor module comprising a chip having first and second major surfaces with areas of metal on the first major surface thereof, a substrate having first and second major surfaces with areas of metal on the first major surface thereof, said chip and substrate being positioned so that the first major surfaces are face to face, and interconnecting joints mechanically connecting and spacing said surfaces, each of said joints being formed of an agglomeration of geometrical shape and material substance with at least two of said interconnecting joints having unequal agglomerations, whereby the stress resistivities for said unequal agglomerations are unequal.

2. The module as claimed in claim 1 wherein each of said interconnecting joints is mechanically joined to one of said areas of metal on said first major chip surface and one of said areas of metal on said first major substrate surface.

3. The module as claimed in claim 2 wherein said two unequal agglomerations are of the same material but have unequal shapes.

4. The module as claimed in claim 2 wherein said two unequal agglomerations are made of solder, one of said two comprising a different volume of solder than the other of said two.

5. The module as claimed in claim 2 wherein said two unequal agglomerations are solder joints and one is substantially fatter than the other.

6. The module as claimed in claim 5 wherein said chip comprises a plurality of electrical circuit elements and some of said areas of metal on said first major chip surface are electrically connected to some of said circuit elements, and wherein said fatter solder joints are connected to an area of metal on said first major chip surface which is not electrically connected to one of said circuit elements.

7. The module as claimed in claim 2 wherein said two unequal agglomerations have different material constituencies.

8. In a semiconductor module formed of a chip mounted to a substrate each having first and second major surfaces the improvement comprising a plurality of solder wettable metal regions on the first major face of said chip, a first plurality of solder wettable metal regions of a first size on the first major face of said substrate, a second plurality of solder wettable metal regions of another size substantially different from the first size on said first major face of said substrate, and plural stress resistant solder means for connecting respective ones of the metal regions on said chip and substrate, whereby said connection means have a first stress resistivity or a second stress resistivity different from the first dependent on whether connection is made to one of said first or second pluralities of wettable regions on said substrate.

9. In the module as claimed in claim 8 wherein the first plurality of said solder wettable metal regions on said substrate are smaller in area than the second plurality of solder wettable metal regions on said substrate.

10. In the module as claimed in claim 8 wherein said second plurality of solder wettable metal regions are positioned near the corners of said module.

11. In the module as claimed in claim 8 wherein said first plurality of solder wettable metal regions are nearer the center of said chip than said second plurality of solder wettable metal regions.

12. In the module as claimed in claim 8 further comprising conductive metal fingers on said substrate in contact with saId solder wettable regions and glass dams overlying said conductive fingers to block solder on said solder wettable regions from flowing onto said conductive fingers.

13. A semiconductor module comprising a first member having first and second major faces thereof, an electrically conductive material on portions of said first major face thereof, a second member having first and second major faces thereof, an electrically conductive pattern on said first major face of said second member including regions of wettable with solder conductive material differing in size and surrounded by non-wettable with solder material, and a plurality of stress resistant solder means for interconnecting and separating said electrically conductive material on said first member with respective ones of said surrounded solder wettable regions on said second member, whereby said solder means have differing stress resistivities dependent on which ones of said surrounds solder wettable regions connection is made to on said second member.

14. The module as claimed in claim 13 wherein said surrounded solder wettable regions further from the center of said first member are larger than said other surrounded solder wettable regions.

15. The module as claimed in claim 13 wherein all of said solder means comprise the same volume of solder and wherein said solder means contacting said smaller surrounded solder wettable regions are fatter than said solder connectors contacting said larger surrounded solder wettable regions.

16. In a semiconductor module formed of a chip mounted to a substrate each having first and second major surfaces, the improvement comprising a plurality of solder wettable metal regions on the first major face of said chip, a plurality of solder wettable metal regions of differing size on the first major face of said substrate, and a plurality of stress resistant solder means for connecting respective ones of the metal regions on said chip and substrate, whereby said connection means have differing stress resistivities dependent on which of said plurality of wettable regions connection is made to on said substrate.

17. A solid state package for monolithic integrated semiconductor structures comprising, in combination, a dielectric substrate;

a plurality of conductive metal land patterns located on a surface of said dielectric substrate;

a plurality of terminal pads a number of which having different cross-sectional areas and in electrical and physical contact with end portions of said plurality of conductive metal land patterns;

a monolithic integrated semiconductor chip supported on and in contact with said terminal pads;

a number of said plurality of terminal pads which have a larger cross-sectional area than the remainder of said terminal pads substantially elevate said chip and provide stress relief for the remainder of said terminal pads, said end portions of said plurality of individual conductive lands defining a parallel sided configuration, two end portions on each side of the four sides of said parallel sided configuration having a smaller width than the remaining end portions on each side.

18. A solid state package in accordance with claim 17 wherein said two smaller width end portions on each side of the four sides of said parallel sided configuration being located substantially in the middle of each side.

19. A solid state package in accordance with claim 17 wherein said two smaller width end portions on each side of the four sides of said parallel sided configuration being located one each at opposite ends of each side.