Variable block length synchronization system
First Claim
1. In a variable block length synchronization system for use in the transmission of digital bits of message information grouped in blocks of highly variable length, counting means for producing an output signal indicative of the number of bits in each block of message information;
- encoding means responsive to the output of said counting means to produce an error correction synchronization word that includes information as to the number of bits in each block of message information; and
means for combining the synchronization words of said encoding means with the variable length blocks of message information to form a digital bit stream wherein each synchronization word precedes a block of message information, each synchronization word serving to indicate the bit-length of the succeeding block of message information so that the location of the next successive synchronization word can be determined.
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Abstract
Framing or block synchronization of digital information signals grouped in blocks of variable length is provided by preceding each block with a synchronization code word. Each synchronization code word is error correction encoded in accordance with a BCH code to indicate the number of information bits in the following block and, hence, the location of the next succeeding synchronization code word. Since only the synchronization code words are error correction encoded, they can be distinguished from the information bits to obtain synchronization. A synchronization receiver acquires synchronization upon the occurrence of an error-free synchronization code word in the incoming signal. Synchronization is maintained thereafter by utilizing the inherent error correction capability offered by the BCH code to correct up to two errors in each received synchronization code word before decoding it to locate the next synchronization word. If, however, three errors are detected in a received synchronization word, synchronization is assumed to be lost and synchronization is thereafter recovered with the occurrence of a succeeding error-free synchronization code word in the incoming digital signal. Two receiver embodiments are disclosed which perform the above-described operation. The first embodiment is adapted to perform a general type of framing synchronization, while the other embodiment is specifically adapted to provide video synchronization.
50 Citations
8 Claims
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1. In a variable block length synchronization system for use in the transmission of digital bits of message information grouped in blocks of highly variable length, counting means for producing an output signal indicative of the number of bits in each block of message information;
- encoding means responsive to the output of said counting means to produce an error correction synchronization word that includes information as to the number of bits in each block of message information; and
means for combining the synchronization words of said encoding means with the variable length blocks of message information to form a digital bit stream wherein each synchronization word precedes a block of message information, each synchronization word serving to indicate the bit-length of the succeeding block of message information so that the location of the next successive synchronization word can be determined.
- encoding means responsive to the output of said counting means to produce an error correction synchronization word that includes information as to the number of bits in each block of message information; and
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2. A synchronization system as defined in claim 1 wherein said error correction synchronization word is encoded in accordance with a (24, 14) Bose-Chaudhuri-Hocquenghem error correction code.
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3. A synchronization system as defined in claim 2 including means for inverting the first bit of each synchronization code word.
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4. A synchronization system as defined in claim 3 wherein said encoding means comprises a shift register having a series of ten register cells and modulo-2 adders interleaved in predetermined positions in said series in accordance with the generator polynominal of said (24, 14) error correction code, said shift register serving to generate the ten parity bits of said (24, 14) error correction code.
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5. A variable block length synchronization system comprising transmitting means for producing a constant rate bit stream of serially alternating error correction encoded synchronization words and variable length blocks of information signals, each one of said synchronization words precediing a block of information signals and serving to indicate the bit-length of the same to thereby locate the position of the next successive synchronization word at the end of the block;
- and means for receiving said bit stream comprising, storage means for delaying the propagation of said bit stream for a period of time equal to the time duration of said synchronization words, shift register means having the input signal and output signal of said storage means applied thereto for producing in response a set of signals indicative of the errors if any present in each synchronization word, logic means for evaluating said set of signals to correct any two errors occurring in each synchronization word, and decoding means coupled to said storage means for evaluating each synchronization word to locate the next successive synchronization word in said bit stream.
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6. A variable block length synchronization system in accordance with claim 5 wherein said receiving means further comprises gating means connected to said shift register means to produce an output signal indicative of the occurrence of an error-free synchronization word in said bit stream as indicated by said set of signals.
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7. A variable block length synchronization system in accordance with claim 6 wherein said receiving means further comprises signal gating means connected to receive the bit stream output of said storage means, and bistable means for producing a control signal for said signal gating means such that said gating means is inhibited for an interval corresponding to the occurrence of synchronization words in said bit stream so as to produce an output signal comprising only blocks of information signals.
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8. A variable block length synchronization system in accordance with claim 7 wherein said decoding means comprises counting means preset in accordance with the location information of each synchronization word for counting at the bit rate of said bit stream during the interval the block of information signals are received to produce an output signal indicative of the end of each block of information signals and thus the location of the next successive synchronization word in said bit stream.
Specification