Simplex ARQ system

• US 3,878,333 A
• Filed: 12/05/1973
• Issued: 04/15/1975
• Est. Priority Date: 12/12/1972
• Status: Expired due to Term

• Current Assignee: Hitoshi Koyano, Otoomi Shimizu
• Original Assignee: Hitoshi Koyano, Otoomi Shimizu
• Inventors: Shimizu, Otoomi, Koyano, Hitoshi
• Primary Examiner(s): Robinson, Thomas A.
• Application Number:
  US05/421,947
• Time in Patent Office: 496 Days
• Field of Search: 178/23A,2A,DIG.3,DIG.12 340/146.1AL,1B,1BA 179/15AE 325/38R,38A,38B
• US Class Current: 178/23.00A
• CPC Class Codes: H04L 1/0007 by modifying the frame length
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems

Abstract

An improved simplex ARQ system for data transmission circuits using a short wave circuit is provided. A block of characters is sent from a master station to a slave station and if an error occurs during the transmission, said block of characters is automatically re-transmitted, thus clean output without an error is obtained on a printer in a receiving or slave station. The length of said block is changed according to the instantaneous quality of the short wave circuit, and thus the actual transmission speed is considerably increased.

Claims

1. A method for transmitting digital data in a simplex ARQ communication system consisting of a master and a slave station comprising the steps of transmitting a block of characters from the master station to the slave station, transmitting a control signal from the slave station to the master station indicating if said block of characters has been transmitted correctly, retransmitting said block of characters in the case where said control signal indicates the preceding block of characters was transmitted incorrectly, characterized in that the number of characters in said block is variable in direct correspondence with instantaneous transmission quality.

2. A method according to claim 1, wherein said number of characters in a block is an integer multiple as large as a predetermined integer.

3. A method according to claim 1, wherein said number of characters in a block is an odd multiple of a basic length.

4. A method according to claim 1, wherein said number of characters in a block is changed according to the quality of the transmission circuit.

5. A simplex ARQ system comprising at least a transmission memory (T MEM) having two series of memories for temporarily storing a block of characters to be transmitted, a receiving memory (R MEM) having two series of memories for temporarily storing a block of received characters, a transmission control (T CONT) for controlling the operation of said transmission memory (T MEM), a receiving control (R CONT) for controlling the operation of said receiving memory (R MEM), and a mode switching circuit (MODE) for at least switching said series of memories in the transmission memory (T MEM) and the receiving memory (R MEM).