LSI programmable processor

• US 3,878,514 A
• Filed: 11/20/1972
• Issued: 04/15/1975
• Est. Priority Date: 11/20/1972
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Ulbe Faber
• Inventors: Faber, Ulbe
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/307,863
• Time in Patent Office: 876 Days
• Field of Search: 340/172.5
• US Class Current: 712/200
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/265 by address selection on input of storage

Abstract

A microprogrammable serial byte processor suitable for complete implementation of memory, logic, control and addressing functions on a single integrated circuit chip through large scale integration technology. An instruction set, at the microprogrammable level, is provided for controlling the processor in executing basic computer functions. Each instruction of the instruction set has a unique format which is decoded and executed by a circuit design that initially represents minimally committed logic or hardware, and which becomes committed to a specific task by control signals which are decoded from the formatted instructions. Specific circuitry for executing serially by bit the individual instructions of the instruction set is maintained at a simple and minimal level by employing a soft mechine architecture with a microprogramming approach.

Claims

1. An apparatus for processing data in accordance with a stored program comprising:

memory means for storing a plurality of microinstructions, each of said microinstructions including control information;

a serial input bus for receiving information bits to be processed;

a serial output bus for transferring processed information bits from said processor;

means connected between said buses and coupled to said memory means for accessing at least one of said plurality of microinstructions and providing said control information; and

at least one logical unit connected between said buses and responsive to said provided control information received in parallel from said means for accessing for serially performing logical operations on information bits received by said input bus.

2. An apparatus according to claim 1 wherein said means for accessing includes:

control means for generating gating pulses;

first means responsive to said control means for selectively retrieving from said memory means said at least one of said plurality of microinstructions from said memory means; and

second means coupled to said first means and responsive to certain of said gating pulses for decoding said retrieved instruction.

3. An apparatus according to claim 2 wherein said first means includes;

a unique serial path connecting said input bus to said output bus, said unique path including a first register for receiving address information bits for said memory means;

a second register connected between said first register and said memory means for addressing said memory means, said second register receiving address information bits in parallel from said first register;

a first parallel path from said second means to said first register, said first parallel path including a selection gate;

a second parallel path from said second register to said selection gate; and

second control means coupled to said selection gate and said first register and responsive to certain of said provided control information for loading in parallel said first register with decoded information provided by said second means or the contents of said second register to allow repeated retrieval of said at least one of said plurality of microinstructions addressed by said second register or to allow retrieval of a microinstruction specified by said at least one of said plurality of microinstructions or for loading serially said first register with address information bits communicated by said unique serial path.

4. An apparatus according to claim 1 wherein said logical unit includes;

first register means connected to said input bus for storing said received information bits within said apparatus;

an arithmetic unit having a first and second input;

first gating means connected between said first register means and said arithmetic unit for selectively communicating said stored received information bits to said first input of said arithmetic unit, said arithmetic unit performing arithmetic manipulations on said stored received information bits;

second register means connected to said second input of said arithmetic unit for storing said manipulated received information bits within sid apparatus; and

second gating means connected between said output bus and said arithmetic unit for selectively communicating said manipulated received information bits from said arithmEtic unit to said output bus or said second register means.

5. A programmable data processor comprising:

a source of microinstructions, each of said microinstructions including control information;

a serial input bus for receiving information bits to be processed;

a serial output bus for transferring processed information bits;

means connected between said buses for selectively retrieving from said source of microinstructions at least one of said plurality of microinstructions;

control means coupled to said source of microinstructions and connected between said buses for providing in parallel said control information by decoding said at least one of said plurality of microinstructions;

an arithmetic unit;

a plurality of serial data paths from said input bus to said output bus, each of said paths including at least one register means and said arithmetic unit; and

means coupled to each of said one register means and responsive to said provided control information received in parallel from said control means for transferring said received information bits to said output bus.

6. In a data processing system including a plurality of input and output registers, an apparatus for processing data in accordance with a stored program comprising:

a serial input bus for receiving information bits to be processed;

a serial output bus for transferring processed information bits;

memory means for storing a plurality of microinstructions, each of said microinstructions having control information;

means coupled to said input bus and said memory means for accessing at least one of said plurality of microinstructions;

means coupled to said memory means and said plurality of input and output registers and responsive to a portion of said control information provided by said at least one of said plurality of microinstructions for controlling transfer of information bits from said plurality of input registers to said input bus and from said output bus to said plurality of output registers; and

a logic unit connected between said buses and coupled to said memory means for performing logical operations on said received information bits responsive to another portion of said control information of said provided at least one of said plurality of microinstructions.

7. An apparatus for processing data in accordance with a stored program comprising:

memory means for storing a plurality of microinstructions, each of said microinstructions including control information, certain of said microinstructions including a data information portion;

a serial input bus for receiving information bits to be processed;

a serial output bus for transferring processed information bits;

address means coupled to said input bus and said memory means for selectively retrieving from said memory means at least one of said plurality of microinstructions, said retrieved at least one of said plurality of microinstructions including said data information portion;

decoding means coupled to said memory means for providing said control and said data information of said retrieved at least one of said plurality of microinstructions;

first register means coupled to said decoding means for storing said decoded data information;

an arithmetic unit;

second register means connected between said input bus and said arithmetic unit for storing said received information bits within said apparatus, said arithmetic unit performing arithmetic manipulations on said stored received information bits; and

gating means connected between said output bus and said arithmetic unit and said first register means and responsive to said provided control information for selectively gating said stored decoded data information from said first register means or said manipulated received information bits from said arithmetic unit to said output bus.

8. A microprogrammable processor comprising:

a source of microinstructions, each of said microinstructions including control information;

a serial input bus for receiving command information and data information bits;

a serial output bus for communicating processed data information bits from said processor;

command means coupled to said input bus and said source of microinstructions and responsive to said received command information for selecting at least one microinstruction from said source of microinstructions; and

a logic unit connected between said buses and coupled to said command means and responsive to said control information of said selected at least one microinstruction for performing logical operations on data information received by said input bus.

9. A microprogrammable processor comprising:

a single semiconductor chip;

said chip having fabricated thereon;

memory means for storing a plurality of microinstructions, each of said microinstructions including control information;

a serial input bus for receiving information bits to be processed;

a serial output bus for communicating processed information bits from said processor;

address means connected to said input bus and said memory means for selectively retrieving from said memory means individual ones of said microinstructions; and

a logic unit connected between said serial buses and coupled to said memory means for performing logical operations on said received information bits in accordance with said control information from each of said individual ones of said microinstructions.