Digital frequency-shift keying receiver

• US 3,879,665 A
• Filed: 06/28/1973
• Issued: 04/22/1975
• Est. Priority Date: 06/28/1973
• Status: Expired due to Term

• Current Assignee: Earl Fred Carlow, Harold Garth Nash
• Original Assignee: Earl Fred Carlow, Harold Garth Nash
• Inventors: Nash, Harold Garth, Carlow, Earl Fred
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/374,594
• Time in Patent Office: 663 Days
• Field of Search: 325/30,45,320,344,349,487 178/66R,66A,67,88 179/2DP,2E 329/104,126,128
• US Class Current: 375/328
• CPC Class Codes: H04L 27/1563 using transition or level detection

Abstract

A digitally implemented frequency-shift keying receiver receives an input periodic oscillation signal of a first frequency, designated a binary '"'"''"'"''"'"''"'"'1'"'"''"'"''"'"''"'"' and of a second frequency, designated a binary '"'"''"'"''"'"''"'"'0'"'"''"'"''"'"''"'"'. A unidirectional pulse is generated each time the input signal passes through a reference voltage, either positive going or negative going. The time between pairs of these pulses is measured by starting a free running counter with a first pulse and by stopping and re-starting the counter with a second pulse. If the time between two of these pulses is sufficiently long, an up-down counter counts in one direction and if the time is sufficiently short, it counts in the other direction. The up-down counter, by providing a prescribed number of counts in either direction to reach a threshold, effectively filters the input signal. An output stage, responsive to the threshold of the updown counter, provides either a binary 1 or a binary 0.

Claims

1. A digital frequency-shift keying (FSK) receiver including shaping means for receiving an input periodic oscillation signal of a first frequency, designated a binary 1 and of a second frequency, designated a binary 0, comprising:

a. threshold detector means connected to the shaping means for producing a plurality of unidirectional pulse position signals whenever a positive going or a negative going portion of the periodic oscillation signal passes through a prescribed potential;

b. timing means connected to said threshold detector means for measuring the time between the pulses produced by the detector means to provide indicia signals representative of whether the input signals are of the 1 or 0 frequency; and

c. oUtput means connected to said timing means and responsive to the indicia signals for providing on a single output line an output pulse of one polarity if the input signal is at the binary 1 frequency and an output pulse of the opposite polarity if the input signal is at the binary 0 frequency.

2. The FSK receiver of claim 1 wherein said timing means further comprise:

a. resettable counter means connected to said threshold detector means for counting digital pulses of a predetermined frequency in response to a first pulse position signal, and being responsive to a second pulse position signal for resetting to a first predetermined state, said resettable counter means being responsive for generating a counter output signal upon reaching a predetermined count, b. indicia signal generating means connected to said resettable counter means and being responsive to the counter output signal for providing an indicia signal of a polarity representative of a binary 1 upon the generation of a counter output signal, and for providing an indicia signal of a polarity representative of a binary 0 in the absence of a counter output signal.

3. The FSK receiver of claim 1 wherein the output means further comprise:

a. up-down counting means connected to said indicia signal generating means and being responsive to the indicia signals for counting in one direction when the indicia signal represents a binary 1 input signal and in the other direction when the indicia signal represents a binary 0 input signal;

b. threshold decoding means connected to said up-down counting means for providing a first voltage level representative of a binary 1 input in response to a predetermined count from the up-down counting means in one direction, and for providing a second voltage level representative of a binary 0 input in the other direction; and

c. bistable output means connected to said threshold decoding means for providing a binary 1 output when set by the first voltage level and a binary 0 ouput when set by the second voltage level.

4. The FSK receiver of claim 2 wherein the output means further comprise:

a. up-down counting means connected to said indicia signal generating means and being responsive to the indicia signals for counting in one direction when the indicia signal represents a binary 1 input signal and in the other direction when the indicia signal represents a binary 0 input signal;

b. threshold decoding means connected to said up-down counting means for providing a first voltage level representative of a binary 1 input in response to a predetermined count from the up-down counting means in one direction, and for providing a second voltage level representative of a binary 0 input in the other direction; and

c. bistable output means connected to said threshold decoding means for providing a binary 1 output when set by the first voltage level and a binary 0 output when set by the second voltage level.

5. The FSK receiver of claim 2 wherein the resettable counter means further comprise:

a binary counter for counting the digital pulses, a decoding circuit connected to the binary counter and to said indicia signal generating means for producing a binary counter output signal when the binary counter reaches the predetermined count, and said indicia signal generating means being responsive to said binary counter output signal.