Temporary memory for time division multiplex telephony system exchanges

• US 3,885,104 A
• Filed: 07/02/1973
• Issued: 05/20/1975
• Est. Priority Date: 09/25/1972
• Status: Expired due to Term

• Current Assignee: Herman Deutsch, William Ralph Smith
• Original Assignee: Herman Deutsch, William Ralph Smith
• Inventors: Deutsch, Herman, Smith, William Ralph
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/375,790
• Time in Patent Office: 687 Days
• Field of Search: 179/15AT,15A,15AL,15AQ,18ES,18AD,18AA,18J 340/172.5
• US Class Current: 370/377
• CPC Class Codes: G04F 10/04 by counting pulses or half-cycles of an ac G04F10/005 takes precedence
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits
• CPC Class Codes: H04M 3/561 by multiplexing
• CPC Class Codes: H04M 3/58 Arrangements for transferring received calls from one subscriber to another; Arrangements affording interim conversations between either the calling or the called party and a third party substation line holding circuits H04M1/80
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

Information relating to interconnections made through the time division switch of a telephony exchange is recorded in binary form in a plurality of memory elements. This information includes addresses permanently assigned to interconnected equipment, the on- or off-hook status of the equipment, and the status of the connection established through each time slot. The recorded information is made to recirculate and is read out periodically to provide gating information to the time division switch.

Claims

1. In a time division switching private automatic branch exchange, a temporary memory for providing constantly updated information concerning the connection established within each time slot comprising a plurality of equal length recirculating shift registers each having at least one bit position for each recurring time slot and a common clock pulse source connected to each shift register to advance all such shift registers in synchronization, a first group of said shift registers defining at least two address fields for recording binary information identifying the equipment interconnected through each time slot, and a second group of shift registers including at least one storage element associated with each address field for recording therein the on-hook or off-hook status of equipment identified by that field.

2. The apparatus of claim 1, wherein said first group of shift registers defines at least three address fields.

3. The apparatus of claim 1, wherein a third group of said shift registers defines a tag field for binary information indicating which of a plurality of conditions exists with respect to each time slot, said conditions including ringing, hold, dialing, and active interconnection for audio purposes.

4. A memory device for use in a time division multiplex exchange comprising a multiplicity of sets of binary storage elements for containing in each set information relating to one time slot of the system, each set including an address portion in which at least two addresses uniquely assigned to individual pieces of equipment interconnected through that time slot can be recorded in different address fields, an off-hook portion in which the on or off-hook status of each of said pieces of equipment can be recorded and a tag portion in which information relating to the status of the connection can be recorded, a clock pulse source, and means for reading from the storage elements in a circulatory manner the information relating to each time slot in sequence.

5. The apparatus of claim 4, wherein said address portion includes three address fields.

6. The apparatus of claim 5, wherein said off-hook portion includes one storage element for each address field.

7. The apparatus of claim 4, further comprising means for causing the information recorded in the storage elements to be periodically transposed from one set to the next as the information is read out.