Synchronous data channel for pulse code modulation communications system

• US 3,886,317 A
• Filed: 12/17/1973
• Issued: 05/27/1975
• Est. Priority Date: 12/17/1973
• Status: Expired due to Term

• Current Assignee: Paul E. Drapkin
• Original Assignee: Paul E. Drapkin
• Inventors: Drapkin, Paul E.
• Primary Examiner(s): Blakeslee, Ralph D.
• Application Number:
  US05/425,215
• Time in Patent Office: 526 Days
• Field of Search: 179/2DP,3,15BY,15BM,15BS,15A,15BV 340/69.5R,172.5
• US Class Current: 370/522
• CPC Class Codes: H04J 3/1647 Subrate or multislot multiplexing
• CPC Class Codes: H04J 3/172 Digital speech interpolation, i.e. DSI
• CPC Class Codes: H04L 5/22 using time-division multiplexing

Abstract

One voice channel of a T1 PCM terminal of an exchange carrier system is replaced with a synchronous channel unit which may be run at various data rates with a clock which is supplied internally utilizing the basic clock repetition rate of the PCM system. This internal clock is derived by removing selected bits and counting down digitally.

Claims

1. A pulse code modulation (PCM) communications system for transmitting information from a plurality of channels such system including a framing bit some of said channels being for transmission of voice type data but at least one channel being exclusively for synchronous digital input data from a single external source of data the repetition rate of transmitted pulses being a predetermined clock frequency said system including a channel counter generator for determining said plurality of channels comprising:

clock generator means for receiving said clock frequency and for deriving therefrom a signal for timing said synchronous digital data input said clock generator means being responsive to said framing bit for removing at least one bit from said clock frequency for deriving said timing signal;

means for connecting said clock generator means to said external source of data to couple said timing signal to said source of data for providing synchronous operation;

storage register means for storing said digital data; and

gating means responsive to the channel counter generator counting to said one channel for transferring said stored data to a PCM transmit bus.

2. A PCM system as in claim 1 where said clock frequency is 1.544 MBit/sec and said framing bits have a frequency of 8 KBit/sec.

3. A system as in claim 1 where said clock generator means includes means for symmetrically removing two out of eight bits from said clock frequency to provide a substantially symmetrical timing signal.

4. A system as in claim 1 where said clock generator means includes means for removing selected bits and dividing to provide a substantially symmetrical timing signal.

5. A system as in claim 4 together with means for receiving an external transmit clock and shift register means included in said storage register means and shift register means for receiving corresponding data the shift right input of said shift register being clocked by a divided signal from said clock generator means, and pulse comparator means for providing a timing difference between said divided signal and said external transmit clock.

6. A system as in claim 1 where said storage register means includes shift register means for receiving said serial input data at a rate proportional to said synchronous rate of said timing signal and converting it to parallel format and including parallel storage means coupled to said gating means and shift register means whereby said serial input data is bunched into a serial format for transmission on said PCM buss at said clock frequency repetition rate.

7. A system as in claim 1 where said storage register means includes shift register means for receiving said input data such shift register having a shift right input timed by a signal proportional to said timing signal.

8. A system as in claim 7 where said input signal is asynchronous having a data rate of 10 percent or less than said shift signal.

9. A system as in claim 1 where said storage register means includes shift register means for receiving said input data and converting it to parallel format such register providing an additional bit for use as a low data rate asynchronous data channel.

10. A system as in claim 9 together with parity generator means coupled to said shift register means for generating a parity check bit.

11. A system as in claim 10 including test switch means for reversing said parity check bit.

12. A method of transmitting at least one channel of synchronous digital input data from a single external source of data in a pulse code modulation (PCM) communications system which includes a plurality of channels for transmission of voice type data, the repetition rate of the transmitted PCM pulses being a predetermined clock frequency a group of channels comprising a frame and including a framing bit the method comprising the following steps:

generating a plurality of data rates for selectively synchroNizing digital input data having a predetermined data rate by the steps of removing said framing bit from each of said frames of said clock frequency, thereafter removing two of every eight bits of said above signal and thereafter dividing said above signal to provide a plurality of data rates and timing said digital input data with a selected one of said plurality of data rates.

13. A method as in claim 12 where in said step of removing two of every eight bits, every fourth bit is removed.

14. A pulse code modulation (PCM) communications system for transmitting over a common PCM transmit bus information from a plurality of channels such system including a framing bit, some of said channels being for transmission of voice type data but at least one channel being exclusively for synchronous digital input data from a single external source of data the repetition rate of transmitted pulses being a predetermined clock frequency derived from common equipment both in the transmit and receive portions of said PCM system said system comprising:

transmit means including clock generator means for receiving the clock frequency from the transmit portion of said PCM system and for deriving therefrom a signal for timing said synchronous digital input data said clock generator means being responsive to said framing bit for removing at least one bit from said clock frequency for deriving said timing signal and including means for transferring said timed digital data to said PCM transmit bus within the time boundary of said one channel;

means for connecting said clock generator means to said external source of data to couple said timing signal to said source of data for providing synchronous operation; and

receive means for receiving said digital data transmitted on said PCM bus and including clock generator means for receiving the clock frequency from the receive portion of said PCM system and for deriving therefrom a signal for converting said received digital data from said one channel to a continuous serial pulse train having said synchronous rate.