Method and apparatus for limiting charge of a storage battery charged at a constant voltage

• US 3,889,172 A
• Filed: 10/11/1973
• Issued: 06/10/1975
• Est. Priority Date: 10/13/1972
• Status: Expired due to Term

• Current Assignee: Daniel Lelaidier, Jean Quobex
• Original Assignee: Daniel Lelaidier, Jean Quobex
• Inventors: Lelaidier, Daniel, Quobex, Jean
• Primary Examiner(s): Miller, J. D.
• Assistant Examiner(s): Hickey, Robert J.
• Application Number:
  US05/405,636
• Time in Patent Office: 607 Days
• Field of Search: 320/35,39,40,48,23,20,31 317/50,33C,29,9B,36TD
• US Class Current: 320/156
• CPC Class Codes: H02J 7/00718 in response to charge current gradient

Abstract

Method for charging, at a constant voltage, a storage cell battery liable to thermal runaway at the end of charge. The charge current is lowered or shut off at the instant when the derivative of the charge current as a function of the time uses above a predetermined value. This method enables avoidance of all thermal racing phenomena applied to alkaline storage cell batteries, intended more particularly for aircraft. Analog processing and logic processing circuits for signals derived from measurement circuits of the charge current of the battery connected with charge feeding of the battery for control of the charge current are described.

Claims

1. Method for limiting the charge of a storage battery comprising charging the battery at a constant voltage, measuring the derivative of the current with respect to time and limiting charge of the battery in response to said derivative upon said derivative reaching a predetermined positive value.

2. Method according to claim 1, wherein said derivative for limiting charging current to the battery is assimilated to a determined value of the ratio between the finite variation of the charge current during a short period and said period, said current variation being definable by a proportional voltage variation.

3. Method according to claim 2, wherein limiting of charge current to the battery being charged by said current becomes effective only when said ratio is maintained above said determined value during a given interval of time.

4. Method according to claim 3, wherein said determined value is derived by determining the value of a corresponding variation of voltage proportioned to the intensity of the charge current.

5. Method according to claim 4 wherein said value of said variation of voltage is determined by analog comparison.

6. Method according to claim 5 wherein said analog comparison embodies comparing continuously a true voltage measured at a point at a given instant of time with voltage obtained with a given delay.

7. Method according to claim 5 wherein said analog comparison comprises comparing voltage during determined periods of time to voltage proportional to charging current.

8. Method according to claim 4 wherein said value of said variation of voltage is determined by logic comparison.

9. Method according to claim 8 wherein said logic comparison comprises transforming said variation in voltage into pulses whose frequency is proportional to said voltage.

10. A systeM for charging storage cells at constant voltage comprising means for supplying a charging current at constant voltage to such cells, means for limiting charge of the cells, means for measuring the derivative of the charge current with respect to time, and means responsive to said derivative reaching a predetermined positive value for then actuating said means for limiting charge of the cells.

11. A system according to claim 10, wherein said means for limiting charge of the battery comprises means for assimilating said derivative to a determined value of the ratio between finite variations of the charge current during a short period and said period, and defining said variation by a proportional voltage variation.

12. A system according to claim 11 including means whereby limiting of charge current to the battery being charged by said current becomes effective only when said ratio is maintained above said determined value during a given interval of time.

13. A system according to claim 11 including means for deriving said determined value in response to a variation in voltage proportion to the intensity of said charge current.

14. A system according to claim 13 wherein said means for deriving said determined value is an anolog comparison means.

15. A system according to claim 14 wherein said analog comparison means comprises means for comparing continuously a true voltage at a point at a given instant of time with voltage obtained with a given delay, and a capacitor-resistor containing circuit for introducing said given delay.

16. A system according to claim 14 wherein said analog comparison means comprises two capacitors subjectable during determined periods of time to voltage proportional to charging current.

17. A system according to claim 13 wherein said means for deriving said determined value of said variation in voltage is a logic comparison means.

18. A system according to claim 17 wherein said logic comparison means comprises means for transforming said variation in voltage into pulses whose frequency is proportional to said voltage.

19. A system for charging storage cells at a constant voltage comprising power supplying circuit means for supplying charging current at constant voltage to such cells and charge control circuit means for controlling and limiting charge of the battery when the derivative of charge current in relation to time rises above a determined value, said power supply circuit means including rectifier means connected thereto, switch means between the power circuit means operable to connect or disconnect said power circuit means and said storage cells, transducer means in said power supply circuit for measuring charge current at a voltage which is a function of said charge current, and said charge control circuit means comprising amplifier means for voltage derived from said transducer means, differentiator means connected to receive amplified voltage from said amplifying means, comparator means connected to receive output flow from said differentiator means and integrator means connected to receive output from said differentiator means, output indicating and sensing means connected to receive output of said integrator means, a second switch means, a feed circuit connectable in said power supply circuit by said second switch means for powering said amplifier means, said differentiator means and said output and sensing means, said output and sensing means controlling said two switch means, a third switch means also controlled by said output and sensing means, an integrated operational amplifier means including a negative reaction circuit means to provide a precise voltage gain and cancel the alternate component so as to measure average charging current, a stabilized voltage source to feed said integrated operational amplifier means, said stabilized voltage source including multi-vibrator means oscillating at a stable frequency and a pair of capacitors respectively charged during conductivity periods of said multi-vibrator mEans and discharged during blocked periods of said multi-vibrator means connected to the stabilized voltage source, and said second switch means serving to cut off said stabilized voltage source to said integrated operational amplifier means at the same time as said power supply circuit means in said battery is cut off.

20. A system according to claim 19 wherein said transducer means comprises a shunt connected to said integrated operational amplifier.

21. A system according to claim 19 wherein said multi-vibrator means comprises a network, a pair of transistors interconnected with said network for oscillating at a stable frequency, said pair of capacitors being connected to be respectively charged during conductive periods of said transistors and to discharge into said stabilized voltage source during blocked periods of said transistors.

22. A system according to claim 21 including filtering capacitors and zener diode means connected to stabilize said frequency of oscillation.

23. A system according to claim 19 including reconnecting means to restore connections at said switch means respectively subsequent to cut-off operation thereof.

24. A system according to claim 19 wherein said amplifier means, said differentiator means, said comparator means, said integrator means and said output indicating and sensing means are connected in an analog circuit, said analog circuit including filter means including a capacitor connected to receive output from said amplifier means to provide a fixed voltage, a second capacitor and a resistor connected thereto to provide a different voltage at terminals of said second capacitor providing said differentiator means so that when said first voltage does not vary, said second voltage is equal thereto when said first voltage increases, said second voltage is less than said first voltage and when said first voltage decreases, said second voltage is greater than said first voltage.

25. A system according to claim 24 wherein said comparator means comprises an integrated operational amplifier having an impedance very greatly larger relative to said resistor.

26. A system according to claim 24 including means to apply an adjustable reference voltage as a second input to said compactor means including a resistor, an amplifier and a transistor connected to provide said reference voltage across said resistor by passage through it of a constant current via said transistor and monitored by said last-named amplifier so that said last-named amplifier fires when the difference between said second-named voltage and said first voltage equals a reference value corresponding to that instant at which the derivative of said charge current in relation to time surpasses a determined positive value.

27. A system according to claim 24 wherein said comparator means is adjustable so that said last-named amplifier fires when the difference between said second voltage and said first voltage acquires a reference value corresponding to the instant at with a derivative of charge current in relation to time surpasses a determined positive value.

28. A system according to claim 24 including an integrator-time delay circuit to which output of said comparator current is connected.

29. A system according to claim 28 wherein said integrator-time delay circuit comprises an amplifier adapted to transmit a linear voltage ramp whose value increases negatively, a pair of resistors constituting a voltage divider, an amplifier, a transistor and a switch controlling relay connected together so that when said last-named amplifier is fired by attainment of equality of said ramp voltage and the voltage across said voltage divider, said last-named transistor is blocked to initiate a circuit opening operation of said relay at a determined time after firing of said last-named amplifier enabling elimination of transistory variations in charge current.

30. A system according to claim 19 including logic means for controlling signal output of said amplifier means.

31. A system according to claim 30 wherein said logic means includes conversion circuit means for converting voltage data output of said amplifier means into frequency pulses proportional to charge current of said system.

32. A system according to claim 31, including said flip-flop means, a differential circuit comprising a first counter, a second counter and clock means, said clock means emitting pulses of a determined frequency, and wherein said pulses proportional to charge current of said system are connected to and stored in said first counter for a given period of time, means for transmitting and storing said last-named pulses to said second counter during a period of time equal to said first-named period of time so that when the number of pulses transmitted and stored in said second counter equals the number stored in said first-named counter extra pulses transmitted to said first-named counter are transmitted simultaneously to said second-named counter, a comparator, a second flip-flop, a second comparator comprising a third counter connected to receive said extra pulses when the pulses received by said first and second counters are equal, integrator circuit means responsive to a determined number of pulses received by said third counter and operative to emit a signal at such occurrence, and a control means operative only when said signal from said integrator reaches said control means.

33. A system according to claim 31 wherein said conversion circuit means emits as its output pulses whose frequency varies with the value of the said charge current.

34. A system according to claim 33 including means responsive to attainment of equality of the number of pulses stored to the number of pulses delivered to said means to initiate delivery of a control signal for controlling charge current delivered by said system.