Digit mask logic combined with sequentially addressed memory in electronic calculator chip

• US 3,892,957 A
• Filed: 09/24/1973
• Issued: 07/01/1975
• Est. Priority Date: 09/24/1973
• Status: Expired due to Term

• Current Assignee: John D. Bryant
• Original Assignee: John D. Bryant
• Inventors: Bryant, John D.
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/400,473
• Time in Patent Office: 645 Days
• Field of Search: 235/156 340/172.5
• US Class Current: 708/190
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G06F 15/02 manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators
• CPC Class Codes: G11C 17/126 Virtual ground arrays

Abstract

An electronic calculator system implemented in an MOS/LSI semiconductor chip having a data memory in the form of a sequentially-addressed array of memory cells, and timing masks are generated in a logic array which is interleaved with the sequential address lines of the data memory. A shift register for receiving a part of an instruction word for defining timing masks may be also interleaved with the sequential address lines. The logic array generates any one of a number of timing masks for controlling the gating of data into an arithmetic unit and other functions, dependent upon the instruction word.

Claims

1. An electronic calculator system of the type implemented in monolithic semiconductor means, comprising data memory means having an array of memory cells addressed in sequence, an arithmetic unit for executing operations on data from the memory means, a read-only-memory for storing a large number of instruction words to define the operation of the system, storage means for receiving a part of an instruction word for defining a timing mask, a logic array connected to the storage means and responsive to said part of the instruction word and also connected to receive timing singals used to address the data memory in sequence, the logic array producing one of a plurality of different timing masks in accord with said part of the instruction word, and means for coupling the data memory to the arithmetic unit responsive to the timing masks.

2. An electronic calculator system according to claim 1 wherein a commutator is used to generate timing signals for addressing the data memory in sequence, and the logic array is connected to receive the timing signals from the commutator.

3. An electronic calculator system according to claim 2 wherein a plurality of parallel conductors are used to connect the commutator to the data memory and the logic array is interleaved with said conductors.

4. An electronic calculator system according to claim 3 wherein the storage means is a multi-stage shift register with stages interleaved with said conductors.

5. Apparatus for generating timing masks in an electronic calculator system of the type controlled by instruction words stored in a read-only-memory and having a data memory in the form of a sequentially addressed array of memory cells, comprising means for temporarily storing bits of an instruction word defining a code for a timing mask, programmable logic array means connected to receive the temporarily stored bits as inputs and also connected to receive sequential addressing signals for the array of memory cells and functioning to produce one of a plurality of different timing masks depending upon the instruction word.

6. Apparatus for generating timing masks according to claim 5 wherein the data memory is sequentially addressed once during an instruction cycle time of the calculator system and the timing masks are shorter than said cycle time.

7. Apparatus for generating timing masks according to claim 6 wherein an arithmetic unit is provided in the calculator system and the timing masks are used to control gating of data from the data memory into the arithmetic unit.

8. Apparatus for generating timing masks according to claim 7 wherein the read-only-memory, the data memory, the arithmetic unit, and the logic array means are all located in a monolithic semiconductor unit.

9. Apparatus for generating timing masks according to claim 8 wherein the data memory is addressed in sequence by timing signals generated in a commutator which is connected to the data memory by a plurality of parallel conductors, and said programmable logic array is interleaved with the conductors.

10. Apparatus for generating timing masks according to claim 9 wherein the means for temporarily storing bits includes a shift register having a plurality of stages interleaved with said conductors.