Complementary MIS integrated circuit device on insulating substrate

• US 3,893,155 A
• Filed: 06/17/1974
• Issued: 07/01/1975
• Est. Priority Date: 10/12/1973
• Status: Expired due to Term

• Current Assignee: Katsumi Ogiue
• Original Assignee: Katsumi Ogiue
• Inventors: Ogiue, Katsumi
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Munson, Gene M.
• Application Number:
  US05/480,293
• Time in Patent Office: 379 Days
• Field of Search: 357/23,41,42
• US Class Current: 257/331
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: Y10S 148/051 Etching
• CPC Class Codes: Y10S 148/053 Field effect transistors fets
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

A complementary MIS integrated circuit device comprises an insulating substrate which can precipitate a simple substance material, a monocrystal silicon layer which is formed on the insulating substrate, semiconductor regions which are formed on two sides within the silicon layer and which constitute longitudinal type p-channel and n-channel MISFETs on the respective sides, a notch which is formed between the semiconductor regions on both sides and which extends down to the insulating substrate, gate insulating films which are formed on the side surfaces of the notch, and a gate electrode which is formed on the gate insulating films and the exposed part of the insulating substrate and which is common to both the MISFETs, whereby a p-channel MISFET and a n-channel MISFET are formed to provide a complementary circuit.

Claims

1. A semiconductor device comprising:

an insulating substrate;

a first semiconductor layer of one of a first conductivity type and a second conductivity type disposed on a first portion of said substrate;

a second semiconductor layer of said first conductivity type disposed on a second portion of said substrate spaced apart from said first portion of said substrate, the side surface of said second semiconductor layer facing the opposite side surface of said first semiconductor layer;

a third semiconductor layer of a second conductivity type, opposite said first conductivity type, disposed on said first semiconductor layer and having a side surface contiguous with the side surface of said first semiconductor layer;

a fourth semiconductor layer of said second conductivity type disposed on said second semiconductor layer and having its side surface contiguous with the side surface of said second semiconductor layer;

a fifth semiconductor layer of said first conductivity type disposed on said third semiconductor layer and having its side surface contiguous with the side surface of said third semiconductor layer;

a sixth semiconductor layer of said first conductivity type disposed on said fourth semiconductor layer and having its side surface contiguous with the side surface of said fourth semiconductor layer;

a seventh semiconductor layer of said second conductivity type disposed on said fifth semiconductor layer and having its side surface contiguous with the side surface of said fifth semiconductor layer;

a first insulating film formed along the side surfaces of said first, third, fifth and seventh semiconductor layers;

a second insulating film formed along the side surfaces of said second, fourth, and sixth semiconductor layers; and

a layer of electrode material formed on each of said first and second insulating films.

2. A semiconductor device according to claim 1, wherein said sixth and seventh semiconductor layers are electrically connected to each other.

3. A semiconductor device according to claim 2, wherein said third and fifth semiconductor layers are electrically connected together.

4. A semiconductor device according to claim 3, wherein said second and fourth semiconductor layers are electrically connected together.

5. A semiconductor device according to claim 4, wherein said electrically connected second and fourth layers and said electrically connected third and fifth layers are connected to respectively different sources of reference potential.

6. A semiconductor device according to claim 1, wherein said first semiconductor layer is of said first conductivity type.

7. A semiconductor device according to claim 1, wherein said first semiconductor layer is of said second conductivity type.

8. A semiconductor device according to claim 1, wherein said layer of electrode material is a layer of semiconductor material.

9. A complementary MISFET integrated circuit device comprising:

a monocrystal silicon layer formed on an insulating substrate capable of precipitating a simple substance material;

semiconductor layers which are formed on two sides within said silicon layer and which constitute a p-channel MISFET and an n-channel MISFET of the longitudinal type on respective ones of said two sides, said two side surfaces being formed between said semiconductor layers on both sides and which reach said insulating substrate;

gate insulating films which are formed on said side surfaces; and

a common gate electrode which is formed on said gate insulating films;

whereby a complementary circuit is made up of said p-channel MISFET and said n-channel MISFET.

10. A semiconductor device comprising:

a substrate of insulating material;

a first plurality of semiconductor layers disposed one on top of another on a first portion of said insulating substrate, at least three adjacent ones of which have respectively different conductivity types;

a second plurality of semiconductor layers disposed one on top of another on a second portion of said insulating substrate, and at least three adjacent ones of which have respectively different conductivity types, said second plurality of layers being spaced apart from said first plurality of layers and having side surfaces thereof facing side surfaces of said first plurality of layers;

first and second insulating films disposed on the respective side surfaces of said first and second pluralities of semiconductor layers; and

a common electrode layer disposed on said first and second insulating films.

11. A semiconductor device according to claim 10, wherein said at least three adjacent layers of said first plurality of semiconductor layers have N, P, and N conductivity types respectively, while said at least three adjacent layers of said second plurality of semiconductivity layers have P, N, and P conductivity types, respectively.

12. A semiconductor device according to claim 10, wherein a selected one of said first plurality of semiconductor layers is connected to a selected one of said second plurality of semiconductor layers.

13. A semiconductor device according to claim 10, wherein two adjacent layers of said at least three adjacent layers of said first plurality are electrically connected together.

14. A semiconductor device according to claim 13, wherein two adjacent layers of said at least three adjacent layers of said second plurality are electrically connected together.

15. A semiconductor device according to claim 14, wherein said two adjacent layers of said first plurality are connected to a first source of reference potential, while said two adjacent layers of said second plurality are connected to a second source of reference potential different from said first source.

16. A semiconductor device according to claim 10, wherein two adjacent layers of said at least three adjacent layers of said second plurality are electrically connected together.

17. A semiconductor device according to claim 10, wherein said first plurality of semiconductor layers further includes a fourth semiconductor layer of a conductivity type opposite to the conductivity type of that layer of said at least three layers to which it is adjacent.

18. A semiconductor device according to claim 10, wherein said first plurality of said semiconductor layers further includes a fourth semiconductor layer of a conductivity type the same as the conductivity type of that layer of said at least three layers to which it is adjaceNt.

19. A semiconductor device comprising:

a substrate of insulating material;

a first semiconductor layer at least a portion of which is of a first conductivity type formed on said substrate;

a second semiconductor layer of a second conductivity type, opposite said first conductivity type, formed on said first semiconductor layer and defining a first PN junction with said at least a portion thereof;

a first semiconductor region of said first conductivity type disposed in said second semiconductor layer and defining a second PN junction therewith;

a second semiconductor region of said second conductivity type disposed in said first semiconductor region and defining a third PN junction therewith;

a groove extending through said regions and said layers to the surface of said substrate, so as to separate said regions and layers into first and second separate portions, side surfaces of which are defined by said groove, with each of said first, second and third PN junctions terminating at said side surfaces of said groove, said first portion containing each of said layers and regions and said second portion containing only said first and second layers and said first region;

first and second insulating films disposed on the side surfaces of said groove at which said PN junctions terminate; and

a common electrode layer formed on each of said first and second insulating films.

20. A semiconductor device according to claim 19, wherein said second semiconductor region of said first portion is electrically connected to said first semiconductor region in said second portion.

21. A semiconductor device according to claim 20, wherein said second semiconductor layer is electrically connected to said first semiconductor region in said first portion and to said first semiconductor layer in said second portion.

22. A semiconductor device according to claim 22, wherein said second semiconductor layer is connected to a first source of reference potential in said first portion and to a second source of reference potential, different from said first source of reference potential, in said second portion.

23. A semiconductor device according to claim 19, wherein said second semiconductor layer is electrically connected to said first semiconductor region in said first portion and to said first semiconductor layer in said second portion.

24. A semiconductor device according to claim 19, wherein the first portion of said first semiconductor layer is of said second conductivity type.

25. A semiconductor device according to claim 19, wherein the entirety of said first semiconductor layer is of said first conductivity type.