Electronic selection bingo game unit

• US 3,895,807 A
• Filed: 08/09/1973
• Issued: 07/22/1975
• Est. Priority Date: 01/23/1973
• Status: Expired due to Term

• Current Assignee: David Warren Friedman
• Original Assignee: David Warren Friedman
• Inventors: Friedman, David Warren
• Primary Examiner(s): Pinkham, Richard C.
• Assistant Examiner(s): Kramer, Arnold W.
• Application Number:
  US05/387,194
• Time in Patent Office: 712 Days
• Field of Search: 273/138A,1E,139,13AB,134A,135A,135B,136A 340/323
• US Class Current: 463/22
• CPC Class Codes: A63F 3/0645 Electric lottos or bingo games

Abstract

The invention relates to a selection intersection selecting unit for a bingo game. There are 75 unique selection intersections in a bingo game, and this unit permits any one of the intersections to be selected with equal probability. The unit consists of an electronic circuit including a 5 X 15 switch matrix. The circuit further consists of a clock circuit means with a low frequency and a high frequency output, and a counter circuit driven by the output. The low frequency output is much greater than 75 c.p.s. The counter circuit drives the switch matrix, and the high frequency output is applied to the counter only during a low output of the matrix. The counter has two sets of outputs, one set containing 5 outputs and the other 15, and each set is connected to a different axis of the matrix. Thus, after each count, a different intersection of the matrix is selected and removed. The remaining intersections will then also be selectable with equal probability.

Claims

1. An equal probability selection electronic device for a bingo game allowing a human operator to make, by successive operation, the selection of any one of 75 (or fewer, if some are not selectable) unique selection intersections, comprising:

a switch matrix comprised of 75 slide switches arranged in a 5 X 15 Cartesian coordinate form, each slide switch being used to indicate a selection intersection and being individually controllable by the operation of the human operator to define whether or not the slide switch is selectable and lamp indicators operatively positioned to define the intersection selected at the time of selection;

a selector circuit coupled to said switch matrix and comprised of counter circuit means for successively addressing the slide switches;

clock circuit means coupled to said counter circuit means for driving the counter circuit means and providing a clock pulse output having one of a relatively high and relatively low frequency, the relatively high frequency being used only to sweep past any addresses previously selected;

feedback circuit means connected between the switch matrix and the clock circuit means for controlling said clock pulse output such that the clock pulse output is selected to be of low frequency when a selectable slide switch is being addressed and is otherwise selected to be of high frequency; and

selection start switch means arranged to provide, by successive operator use for each desired selection, both a start signal to the clock circuit means for initiating a selection of a slide switch and a stop signal for initiating termination of a selection cycle, the arrangement being such that the clock pulse output may be stopped only when a selectable slide switch is addressed, which occurs at equal time segments of the addressing sequence, regardless of the number of slide switches no longer selectable.

2. A device as recited in claim 1 wherein said clock circuit means has clock frequencies which are asynchronous and further comprising a misselection prevention circuit means operatively coupled and driven by said clock circuit means with a low frequency to inhibit a high frequency for a delay time of 1/(the high frequency output), which eliminates erroneous advancement of the counter circuit means due to the arbitrary phase relationship of the high frequency with respect to the low frequency.

3. A device as recited in claim 1, wherein said clock circuit means comprises a high frequency clock to provide said high frequency output, and a low frequency clock to provide said low frequency output, the low frequency in Hertz being numerically much greater than the number of slide switches, and the high frequency in Hertz being numerically greater than (2N'"'"''"'"') . (low frequency output), where N'"'"''"'"' is equal to 5 X 16 80.

4. A device as recited in claim 3 wherein said clock circuit means has clock frequencies which are asynchronous and further comprising a misselection prevention circuit means operatively coupled and driven by the low frequency clock to inhibit the high frequency clock for a delay time of 1/(the high frequency output), which eliminates erroneous advancement of the counter circuit means due to the arbitrary phase relationship of the high frequency asynchronous clock with respect to the low frequency asynchronous clock.

5. A device as recited in claim 3 further comprising an acquisition request memory operatively coupled to said clock circuit means, a minimum time control circuit means for controlling the minimum operation time of a selection start switch, and inhibit circuit means, said inhibit circuit means including a nand gate for preventing operation of the acquisition request memory until after a currently selected selection intersection has been removed by opening the contacts of the slide switch corresponding to the currently selected selection intersection, one input of said nand gate being connected through an inverter to the feedback circuit means and another input thereof being directly connected to the output of said minimum time control circuit means, the output of said nand gate being connected to said acquisition request memory, said inhibit circuit means being enabled by a change in the signal from said feedback circuit means when the slide switch corresponding to the selected selection intersection is opened, and thereby causing deletion of that selection intersection from future consideration.

6. A device as recited in claim 1 further comprising an acquisition request memory operatively coupled to said clock circuit means, a minimum time control circuit means for controlling the minimum operation time of a selection start switch, and inhibit circuit means, said inhibit circuit means including a nand gate for preventing operation of the acquisition request memory until after a currently selected selection intersection has been removed by opening the contacts of the slide switch corresponding to the currently selected selection intersection, one input of said nand gate being connected through an inverter to the feedback circuit means and anOther input thereof being directly connected to the output of said minimum time control circuit means, the output of said nand gate being connected to said acquisition request memory, said inhibit circuit means being enabled by a change in the signal from said feedback circuit means when the slide switch corresponding to the selected selection intersection is opened and thereby causing deletion of that selection intersection from future consideration.