Memory fault correction system

• US 3,898,443 A
• Filed: 10/29/1973
• Issued: 08/05/1975
• Est. Priority Date: 10/29/1973
• Status: Expired due to Term

• Current Assignee: Robert Mckee Smith
• Original Assignee: Robert Mckee Smith
• Inventors: Smith, Robert McKee
• Primary Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/410,457
• Time in Patent Office: 645 Days
• Field of Search: 340/172.5,146.1BA 235/153AM
• US Class Current: 714/711
• CPC Class Codes: G11C 29/781 combined in a redundant decoder

Abstract

A memory system is disclosed which is internally self-correcting when a memory failure occurs. Upon detection of a memory output error, the bit which is incorrect is automatically identified and the output from the memory column which provided the error bit is inhibited. At the same time, a spare memory column is activated and the information which was initially in the error column is transferred to the now activated spare column. The output of the spare column is then directed into the bit location of the inhibited column.

Claims

1. A computer memory error correction system comprising a memory having n + m columns and p rows, each row having a unique address and wherein under control of an address associated with any said row a word having n bit positions is obtained from said memory, said word composed of one data bit from one of said n columns of said addressed row, means for checking each obtained word from said memory to detect obtained words having error data bits contained therein, means operable in response To a detected error word for determining which bit position of said word is in error, means for marking the column associated with said determined error bit, means operable in response to a detected error word for selecting one of said m columns of said memory, means for establishing within said selected m memory column at each row thereof data bits identical to the data bits in each corresponding row of said marked column, and means for substituting in each obtained word at the bit position of said marked column the data bit from said selected m column for the data bit from said marked column.

2. The invention set forth in claim 1 wherein said checking means includes a parity check circuit.

3. The invention set forth in claim 2 wherein said parity check circuit is operable to check the parity of said obtained word both before and after said substitution of data bits.

4. The invention set forth in claim 1 further comprising an input for supplying data bits to said memory, and wherein said memory column establishing means includes means for directing data bits from said input to said selected spare column.

5. The invention set forth in claim 1 further comprising means for transferring data bits from one memory column to another memory column, and wherein said memory column establishing means includes said data transferring means.

6. The method of rehabilitating a memory comprising the steps of detecting a memory output error in a word read from memory, determining which bit of said word is in error, inhibiting the readout of the memory bit column associated with said determined error bit, selecting a spare memory bit column, establishing within said selected spare memory bit column the correct data bits which were stored within said error bit column, and substituting in said output word at the bit position of said determined error column the data bit from said selected spare column for the data bit from said determined error column.

7. The invention set forth in claim 6 further comprising the step of checking the output word obtained from memory for the purpose of detecting errors therein after said substitution has occurred.