Computer automated radar terminal system

• US 3,900,846 A
• Filed: 01/14/1974
• Issued: 08/19/1975
• Est. Priority Date: 01/14/1974
• Status: Expired due to Term

• Current Assignee: Burt Heacock, John Gibbon, John Strenkowski, Matthew Tutino, Richard Lipnick
• Original Assignee: Burt Heacock, John Gibbon, John Strenkowski, Matthew Tutino, Richard Lipnick
• Inventors: Gibbon, John, Heacock, Burt, Lipnick, Richard, Strenkowski, John, Tutino, Matthew
• Primary Examiner(s): Wilbur, Maynard R.
• Assistant Examiner(s): Montone, G. E.
• Application Number:
  US05/432,885
• Time in Patent Office: 582 Days
• Field of Search: 343/6R,112TC,5EM,5DP,6.5LC,6.5R 340/23,24,27NA
• US Class Current: 342/37
• CPC Class Codes: G01S 1/02 using radio waves G01S19/00 takes precedence
• CPC Class Codes: G01S 13/872 Combinations of primary radar and secondary radar

Abstract

An automated radar terminal system employs primary (noncooperative) and secondary (cooperating transponder) surveillance radar equipment to monitor the ensemble of aircraft disposed within a subject air space. A data acquisition subsystem supplies detected and verified aircraft transponder-emitted beacon messages, and derived parameters which characterize each message such as aircraft range and azimuth, to a data processing subsystem. The central processor and memory structure there included maintain the interrelated target scratch pad, data base and multiple display files for accurately and efficiently presenting flexible combined primary radar video-alpha-numeric displays which typically vary at each of plural controller display stations.

Claims

1. In combination in an automated radar data processing system for displaying alpha-numeric information characterizing beacon wave returns generated by aircraft-mounted transponders within the area of said system responsive to secondary surveillance radar interrogations and a primary surveillance radar video wave produced by non-cooperative reflections from said aircraft;

said system comprising data acquisition means for receiving said beacon wave returns, said data acquisition means including means for providing a regenerated beacon code wave, a digital range wave characterized by a monotonically increasing value related to the time elApsed since the last emitted secondary surveillance radar interrogation, and digital azimuth information corresponding to the orientation of the secondary surveillance radar when the last transponder interrogation pulse was issued therefrom;

data processing means for receiving said signals provided by said data acquisition means; and

display means, including plural displays, for displaying alpha-numeric information supplied thereto by said data processing means and for displaying said primary surveillance radar video wave which is supplied thereto;

said data processing means includes memory means, said memory means including plural storage means each associated with a different one of said displays, each of said plural storage means including plural storage subportions thereof for storing data characterizing the display presentation to be made for different ones of subject aircraft within the area of said system, subportions of said plural storage means relating to a like aircraft being linked together by stored pointers therein, said memory means including main data base storage means therein, said main data base storge means including plural subportions therein each associated with a different one of the aircraft within the area of said system, said subportions of said main data base storge means including linking means for storing the address of a subportion of one of said plural storage means storing the display information with respect to a like aircraft.

2. A combination as in claim 1, wherein said memory means of said data processing means comprises first and second memories, said main data base storage means being included in a first one of said memories, and said plural storage means including said display information being included in a second one of said memories.

3. A combination as in claim 2 wherein said data processing means includes central processor means including means for communicating with each of said first and second memories, and direct access means for connecting said data acquisition means and said plural displays to said second memory.

4. A combination as in claim 1 wherein said data processing means includes a central procesor, and wherein said memory means includes first and second information retaining means, said plural storage means being included within said second information retaining means, and direct memory access means for connecting said data acquisition means and said plural displays to said second information retaining means.

5. A combination as in claim 1 wherein said data acquisition means includes range means responsive to an input range trigger pulse for generating said digital range wave, said range means comprising a range oscillator and a range counter.

6. A combination as in claim 5 further comprising means responsive to said range trigger for initializing the state of said range counter.

7. A combination as in claim 6 wherein said range counter initializing means includes a register, and gating means for presetting said range counter with the contents of said register.

8. A combination as in claim 1 wherein said data acquisition means includes azimuth generating means, and means for supplying an azimuth reference pulse and an azimuth change pulses to said azimuth generating means.

9. A combination as in claim 8 wherein said azimuth reference pulse and azimuth change pulse supplying means includes a synchro-to-reference and change pulse converter.

10. A combination as in claim 8 wherein said azimuth signal generating means comprises an azimuth counter advanced by said azimuth change pulses, and means responsive to each azimuth reference pulse for initializing said azimuth counter.

11. A combination as in claim 10 wherein said azimuth initializing means comprises a register, and gating means responsive to said azimuth reference pulse for presetting said azimuth counter.

12. A combination as in claim 1 wherein said data acquisition means includes a beacon reply circuit.

13. A combinatioN as in claim 12 wherein said beacon reply circuit comprises means for receiving said beacon return wave, means for delaying said beacon return wave, and coincidence means responsive to a direct and delayed beacon return wave signals for signalling when a proper beacon reply message is encountered.

14. A combination as in claim 13 further comprising a beacon clock, and means for sampling the beacon return wave at a relatively high rate given by said beacon clock in synchronization with said beacon clock wave.

15. A combination as in claim 14 further comprising disjunctive logic means for signalling the incidence of a proper beacon message when coincidence is obtained between the direct beacon wave and any of plural selected outputs from said beacon wave delaying means.

16. A combination as in claim 15 wherein said beacon wave delaying means comprises a plural stage shift register cycled by said beacon clock.

17. A combination as in claim 13 further comprising at least one processor, storge shift register means for receiving the beacon wave output of said beacon wave delaying means, beacon reply output shift register means, and means for transferring the contents of said storage shift register means to said beacon reply output shift register means.

18. A combination as in claim 17 wherein said beacon reply output shift register means includes a portion for receiving a measure of said range wave.

19. A combination as in claim 13 wherein said beacon reply circuit includes at least two processors, storage shift register storage means in each of said processors for receiving beacon wave signals, means for commutating information present at the output of said beacon wave delaying means between said plural processors, means for signalling when information is being transferred into the storage shift register of either processor, and garbled message detector means responsive to signals that said plural processors are coincidentally entering information into the storage shift registers thereof at a time when a signal obtains at the output of said beacon wave delaying means for providing a garbled message indication.

20. A combination as in claim 12 wherein said beacon reply circuit includes garbled message detecting means.

21. A combination as in claim 1 wherein said data acquisition means comprises analog decoder means for selctively supplying display marker signals to said display means.

22. A combination as in claim 21 further comprising register means for receiving a return beacon code wave, plural registers loaded with a beacon code, and plural digital comparators each responsive to the contents of said beacon code storing register means, and to the contents of an associated one of said beacon code storing registers for selectively supplying an output signal upon a match therebetween.

23. A combination as in claim 22 further comprising at least one flag-generating voltage marker source, and interconnection means responsive to a match output from one of said comparators for generating an output from said marker source.

24. A combination as in claim 23 further comprising plural distinct marker sources, and wherein said interconnection means comprises matrix means connected between said comparator outputs and said marker sources.

25. A combination as in claim 24 wherein at least one of said marker sources includes an oscillator, a counter advanced by said oscillator, and a decoder connected to said counter.

26. A combination as in claim 25 wherein said decoder includes plural outputs, and disjunctive logic means connected to selected of said decoder outputs.

27. A combination as in claim 26 wherein a subset of said registers include adjustable switch means.

28. A combination as in claim 23 further comprising signal summing means, means connecting the output of said marker source to said summing means, and means connecting the primary surveillance radar video wave to said summing means.

29. A combination as in claim 1 wherein said daTa processing means includes a central processor, said central processor including plural signal interrupt ports, means connecting said data acquisition means to one of said central processor interrupt ports, and means connecting said plural displays to others of said central processor interrupt ports.

30. A combination as in claim 29 wherein said memory means includes a first and second store, said second store including said plural storage means, means connecting said second store for bilateral signal propagation with said central processor, direct memory access means connected to said second store, said direct memory access means including selector data channel multiplexing means comprising a plurality of access ports, said data acquisition means being connected to a first one of said ports for supplying information directly to said second store, and means connecting said plural displays to others of said plural selector data channel multiplexing ports for receiving information from said plural storage means of said second store.

31. A combination as in claim 29 further comprising multiplexing means connected to said central processor controller actuatable signalling means associated with at least one of said plural displays, and means connecting each of said controller signalling means to said multiplexer.

32. A combination as in claim 31 further comprising modem means connecting to said multiplexer.

33. A combination as in claim 31 further comprising peripheral store means connected to said multiplexer.

34. A combination as in claim 1 wherein at least one of said plural display means comprises a cathode ray tube, gross and fine deflection means coupled to said cathode ray tube, first and second deflection sources, switch means for selectively connecting said gross deflection means with said first deflection source, a sweep generator connected to said switch means, and alpha-numeric coordinate position source means connected to said switch means.

35. A combination as in claim 33 wherein said second deflection source comprises alpha-numeric and leader generators, and means for driving said fine deflection means responsive to the output of generator means.

36. A combination as in claim 35 further comprising further switch means synchronized with said switch means for selectively intensity modulating the beam of said cathode ray tube with the primary radar video wave and with outputs from said alpha-numeric and leader generators.

37. A combination as in claim 1 wherein said memory means includes a scratch pad provisional aircraft target store, said store being divided into a plurality of aircraft storage blocks, each of said storage blocks having range storage means, said blocks being ordered by the contents of said range storing means, each of said blocks including storage means for storing a pointer to the block of next larger range.

38. A combination as in claim 1 wherein said memory means comprises first memory means including said main data base storage means, said main data base storage means being sub-divided into storage blocks each associated with a different declared aircraft, said aircraft declared blocks being ordered, each of said blocks including means for storing a pointer to a succeeding storage block.

39. A combination as in claim 38 wherein said first memory means further comprises hash list storage means, said aircraft characterizing blocks of said main data base storing means being subdivided in accordance with a hash code, said hash list storage means storing an address of an element in the corresponding hash list string.

40. A combination as in claim 39 wherein plural of said plural storage means each includes a storage portion associted with each said storage block of said main data base storage means, each of said storage portions including a pointer address to the next following one of said plural storage means, each block of said main data base storage means including means for storing a pointer to one of said pluraL storage means.

41. A combination as in claim 1 wherein said memory means includes scratch pad memory means, said scratch pad memory means including therein plural storage blocks each associated with one or more beacon return waves previously encountered by said system, said data processing means including means for seeking a correlation between each beacon return wave and one of said scratch pad storage blocks.

42. A combination as in claim 41 further comprising means responsive to said correlation seeking means detecting a correlation by updating the contents of said correlated block in said scratch pad memory means.

43. A combination as in claim 42 wherein said data processing means further comprises means responsive to said correlation seeking means not signalling an existing correlation for a beacon return signal for estabishing a new storage block in said scratch pad memory means.

44. A combination as in claim 43 further comprising target declaration and rejecting means for examining said storage blocks of said scratch pad memory means for selectively causing a new entry in said main data base storage means in said memory means.

45. A combination as in claim 1 further comprising primary and secondary surveillance radar means for radiating interrogation pulse in s spatially confined, rotating air space zone.