Speed tolerant recording and recovery system
First Claim
1. In a digital data tape handling system wherein there is included a tape transport mechanism for moving tape over a transducer element;
- an improved data transfer circuit for controlling the transfer of data to or from said transducer element which comprises;
an oscillator means for generating a repetitive clocking signal for clocking the transfer of data through the transfer circuit, said oscillator means having a repetition frequency which varies in accordance with a reference signal applied thereto, reference signal generating means coupled to said tape transport mechanism for generating a reference signal which varies in dependence upon the speed of the tape over the recording head, a threshold circuit coupled to said reference signal generator means for producing a control signal when the speed of the tape exceeds a predetermined fraction of its full speed, and means responsive to said control signal to render said oscillator means operative to clock the transfer of data through said data transfer circuit.
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Abstract
A digital tape handler is disclosed wherein data transfers to or from the tape are permitted to occur at below full tape speed. A first phase-locked oscillator is made to track the tape speed and controls the data transfer to the tape. A second phase-locked oscillator, which also tracks the speed of the tape, controls data transfers from the tape. A tape speed threshold circuit detects the speed of the tape and when the speed exceeds a predetermined fraction of the full tape speed turns the first and second oscillators on. Lower tape acceleration/deceleration rates during the tape starting and stopping operations are made possible by the invention.
26 Citations
7 Claims
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1. In a digital data tape handling system wherein there is included a tape transport mechanism for moving tape over a transducer element;
- an improved data transfer circuit for controlling the transfer of data to or from said transducer element which comprises;
an oscillator means for generating a repetitive clocking signal for clocking the transfer of data through the transfer circuit, said oscillator means having a repetition frequency which varies in accordance with a reference signal applied thereto, reference signal generating means coupled to said tape transport mechanism for generating a reference signal which varies in dependence upon the speed of the tape over the recording head, a threshold circuit coupled to said reference signal generator means for producing a control signal when the speed of the tape exceeds a predetermined fraction of its full speed, and means responsive to said control signal to render said oscillator means operative to clock the transfer of data through said data transfer circuit.
- an improved data transfer circuit for controlling the transfer of data to or from said transducer element which comprises;
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2. The system of claim 1 wherein said oscillator means comprises a first oscillator circuit connected to clock recording data through the data transfer circuit to the tape and a second oscillator circuit connected to clock data recovered from the tape through the data transfer circuit.
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3. The system of claim 2 wherein said first and second oscillator circuits are phase-locked oscillators each of which includes a voltage controlled oscillator section and a phase comparator section, said phase comparator section being operable to generate an error correction voltage for its associated oscillator, and said reference signal generator is coupled to the phase comparator section of said first oscillator to lock its frequency to the speed of the tape.
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4. The system of claim 3 wherein the error voltage derived from the phase comparator of the first phase-locked oscillator is applied to the second phase-locked oscillator to control its frequency.
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5. The system of claim 4 wherein the second phase-locked oscillator includes a summing amplifier for applying the error voltage derived from the associated phase comparator to the associated voltage controlled oscillator and into which the error voltage from the first phase-locked oscillator is fed.
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6. The system of claim 2 wherein said threshold circuit includes means for generating a first control signal for controlling the operation of the first oscillator circuit and a second control signal for controlling the operation of the second oscillator circuit.
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7. The system of claim 6 wherein the last named means produces the first control signal at a first tape speed and the second control signal at a second higher tape speed.
Specification