Multi-channel AC conflict monitor

• US 3,902,156 A
• Filed: 10/07/1974
• Issued: 08/26/1975
• Est. Priority Date: 10/07/1974
• Status: Expired due to Term

• Current Assignee: Eagle Signal Controls Corp.
• Original Assignee: Frank Warren Hill
• Inventors: Hill, Frank W.
• Primary Examiner(s): Habecker, Thomas B.
• Application Number:
  US05/512,874
• Time in Patent Office: 323 Days
• Field of Search: 340/41R,37
• US Class Current: 340/931
• CPC Class Codes: G08G 1/097 Supervising of traffic control systems, e.g. by giving an alarm if two crossing streets have green light simultaneously

Abstract

A circuit is provided for monitoring the signals displayed by a traffic signal system to detect the displaying of conflicting signals to two or more traffic paths. The circuit includes sensors responsive to the energization of the traffic signal lights and logic elements for determining when conflicting signals are displayed. The signal controller can override the monitor circuit to permit certain normally conflicting signal combinations. Additional logic elements in the circuit determine whether overlaps are permissible with the normal signal displays. When the circuit detects a conflict or an improper overlap, it transfers signal light operation from the normal sequencing mode to a flashing mode.

Claims

1. In a traffic control system for controlling traffic movemenT over a plurality of traffic flow paths at least certain of which conflict with one another and having a traffic signal providing right-of-way and stop indications to each traffic flow path and a controller actuating said traffic signal;

a conflict monitor, comprising;

a plurality of detector circuits, each detector circuit being associated with a different one of said traffic flow paths and producing an output signal during the time interval in which said traffic signal displays a right-of-way indication to said traffic flow path;

a plurality of first logic elements, each first logic element being connected to two of said detector circuits to receive the output signals therefrom, the detector circuits connected to any one of said first logic elements being associated with conflicting traffic flow paths, each first logic element producing an output signal whenever both detector circuits connected thereto produce output signals;

a logic network connected to all of said detector circuits to receive the output signals therefrom, said network producing an output signal whenever an output signal is received from at least one detector circuit of a first group of detector circuits and an output signal is received from at least one detector circuit of a second group of detector circuits, each detector circuit of the first group being associated with a traffic flow path which conflicts with each traffic flow path with which the detectors of the second group are associated; and

circuit means for interrupting normal operation of said traffic signal, said circuit means being responsive to the output signals of each of said first logic elements and of said logic network.

2. The conflict monitor of claim 1 further including means actuated by said controller for disabling said logic network.

3. The conflict monitor of claim 1 wherein said logic network includes first and second OR gates receiving, respectively, the output signals of the detector circuits of said first and second groups as input signals and an AND gate receiving the output signals of said OR gates as input signals, the output signal of said AND gate being the output signal of said logic network.

4. The conflict monitor of claim 3 wherein said controller includes means for blocking said OR gate output signals from said AND gate.

5. The conflict monitor of claim 1 wherein said circuit means includes relay means for effecting interruption of said traffic signal operation and a relay actuating circuit responsive to the output signals of said first logic elements and of said logic network.

6. The conflict monitor of claim 5 wherein said relay actuating circuit includes timing means for delaying relay actuation until said last mentioned output signals have been present for a predetermined time interval.

7. The conflict monitor of claim 1 wherein said traffic signal provides overlap displays and said conflict monitor further includes a plurality of additional detector circuits, one additional detector circuit being associated with each overlap display, each of said additional detector circuits furnishing an output signal during the interval in which the corresponding overlap display is actuated;

a plurality of programmable circuits, one programmable circuit being associated with each overlap display, each programmable circuit receiving the output signal of the corresponding additional detector circuit and producing, in response thereto, control signals indicating the permissible combinations of right-of-way indications during the corresponding overlap; and

a second logic network receiving said output signals of each of said first mentioned detector circuits, said output signals of said additional detector circuits and said control signals, said second logic network producing an output signal whenever output signals are received from said first mentioned and said additional detector circuits in the absence of a control signal, said second logic network output signal being sUpplied to said circuit means as an input signal thereto.

8. In a traffic control system for controlling the movement of traffic along a plurality of paths through an intersection with at least certain of said paths being in conflict with one another and having a signal light and a controller actuating the signal light to provide normal and overlap signal indications;

a conflict monitor, comprising;

a plurality of first detector circuits, one circuit being provided for each normal indication and producing an output signal during the time interval in which said normal indication is displayed;

a first logic circuit receiving the output signals of said first detector circuits and producing an error signal whenever at least two first detector circuit output signals corresponding to conflicting traffic movement paths are present;

an output circuit actuated by said error signal and operable to interrupt normal operation of said signal light;

a plurality of second detector circuits, one circuit being provided for each overlap indication and producing an output signal during the time interval in which said overlap indication is displayed;

a plurality of programmable circuits, one programmable circuit being associated with each overlap signal indication and receiving the output signal of the corresponding one of said second detector circuits to produce, in response thereto, control signals indicating the permissible normal signal indications during the respective overlap; and

a second logic circuit receiving the output signals of said first detector circuits, the output signals of said second detector circuits and said control signals, said second logic circuit producing an error signal whenever at least one first detector output signal and at least one second detector output signal are received in the absence a control signal corresponding to the associated normal and overlap indications, said error signal providing an actuating input to said output circuit.

9. The conflict monitor according to claim 8 wherein said first logic circuit includes a plurality of AND gates, each AND gate receiving the output signals of two of said first detector circuits corresponding to conflicting normal indications, the output signal of any AND gate comprising said error signal.

10. The conflict monitor according to claim 9 wherein said first logic circuit further includes at least two OR gates, each OR gate receiving the output signals from a group of said first detector circuits, said groups being mutually exclusive and each normal indication associated with a detector circuit of one group being in conflict with each normal indication associated with a detector circuit of the remaining groups, each OR gate producing an output signal whenever an output signal from at least one detector circuit of the corresponding group is present, and an additional AND gate receiving the output signals of each of said OR gates, said additional AND gate producing an output signal whenever at least two OR gate output signals are present, said AND gate output signal comprising said error signal.

11. The conflict monitor according to claim 10 wherein each of said gates comprises a current type operational amplifier.

12. The conflict monitor according to claim 8 wherein said second logic circuit comprises a plurality of logic networks, one logic network being provided for each overlap indication, each logic network receiving said output signals of each of said first detector circuits and said control signals for the corresponding overlap function and operable to produce an output signal whenever a first detector circuit output signal is received in the absence of the corresponding control signal, and an AND gate for each overlap indication, each of said AND gates receiving the output signal of the corresponding second detector circuit and the corresponding logic network, the output signal of each of said AND gates constituting said error signal.

13. The conflict monitor according to claim 12 wherein each logic network comprises a plurality of first NAND gates, one NAND gate being provided for each normal indication and receiving the output signal of the corresponding first detector circuit as an input signal, each logic network including circuit means normally providing a second input signal to each of said first NAND gates, said programmable circuits being such that said control signals remove the second input signals from the corresponding NAND gates, each network further including an additonal NAND gate receiving the output signals of each of said first NAND gates as input signals, the output signal of said additional NAND gate being the output signal of said logic network.

14. The conflict monitor according to claim 13 wherein each of said gates comprises a current type operational amplifier.

15. A conflict monitor for a traffic control system of the type having a traffic light for displaying normal phase and overlap signals to control traffic movement through an intersection, certain of said normal phase movements being in conflict with one another, said system including a controller operating said traffic light;

the conflict monitor comprising;

a plurality of first input circuits, one input circuit being provided for each normal phase and producing an output signal whenever said normal phase signal is displayed;

a first solid state logic network comprised of a plurality of AND gates each of which receives said output signals of two of said input circuits associated with conflicting phases and producing an output signal whenever said two phases are in conflict;

a second solid state logic network having a pair of OR gates receiving, respectively, said output signals of first and second groups of said input circuits with the groups being arranged so that any one phase of either group is in conflict with any phase of the other group, and an AND gate responsive to the outputs of said OR gates to produce an output signal in the event a conflict occurs between any phase of one group and any phase of the other group;

means under the control of said signal controller for disabling said second logic network in the event a normally conflicting signal indication is to be intentionally displayed;

a relay operable to switch the signal operation from a sequencing mode to a flashing mode;

a timing circuit responsive to the output of each of said AND gates and operable to actuate said relay;

an additional input circuit associated with each overlap function and producing an output signal whenever said overlap indication is being displayed;

a programmable circuit associated with each overlap function, each programmable circuit receiving the output signal of the corresponding additional input circuit and producing, in response thereto, control signals indicating compatible normal phases during the corresponding overlap; and

an overlap monitoring circuit for each overlap function including a solid state logic network receiving the output signals of said first input circuits, the output signals of said additional input circuit associated with the corresponding overlap function and the control signals of said programmable circuit associated with the corresponding overlap function, each overlap monitoring circuit including an AND gate producing an output signal in the event a nonpermissible phase display occurs during said overlap, the output signal of each of these AND gates also providing an actuating input to said timing circuit.