Large scale multi-level information processing system employing improved failsaft techniques

• US 3,905,023 A
• Filed: 08/15/1973
• Issued: 09/09/1975
• Est. Priority Date: 08/15/1973
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Frank Joseph Perpiglia
• Inventors: Perpiglia, Frank Joseph
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Nusbaum, Mark Edward
• Application Number:
  US05/388,551
• Time in Patent Office: 755 Days
• Field of Search: 340/172.5 235/153AK
• US Class Current: 714/6.2
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings

Abstract

A multiprogrammed multiprocessing information processing system having independently operating computing, input/output, and memory modules through an exchange, and interacting with a multilevel operating system designed to automatically makes optimum use of all system resources by controlling system resources and by scheduling jobs in the multiprogramming mix of the processing system. In operation, the operating system insures that all system resources are automatically allocated to meet the needs of the programs introduced into the system as well as insuring the continuous and automatic reassignment of resources, the initiation of new jobs, and the monitoring of their performance. System reliability is achieved by the incorporation of error detection circuit throughout the system, by single-bit correction of errors in memory, by recording errors for software analysis and by modularization and redundacy of critical elements.

Claims

1. A multi-processing modular data processing system including a plurality of peripheral devices comprising:

a plurality of memory modules interconnected by a memory bus to provide a multi-accessable main memory for said system, each of said plurality of memory modules including a memory control unit and at least one memory storage unit, each of said memory control units being connected to said memory bus and including means for detecting errors in the transfer of information between said memory bus and said memory storage unit;

a plurality of central processing modules, each of said plurality of central processing modules including a program control section and a storage section, each of said storage sections being connected to said memory bus and including means for indicating malfunctions internal to said respective processing module and errors related to information transfer between said respective processing module and said main memory;

a plurality of input/output modules, each of said input/output modules including a memory interface unit and a translator unit, said memory interface unit of each of said plurality of input/output modules being connected to said memory bus, said translator unit of each of said plurality of input/output modules being connected to said program control section of each of said processing modules for receiving control information and including means for detecting and reporting malfunctions internal to said respective input/output module and errors related to information transfers between said respective input/output module and said plurality of peripheral devices;

a maintenance bus coupled to each of said memory control units of said plurality of memory modules and to each of said storage sections of said plurality of central processing modules and to each of said memory interface units of said plurality of input/output modules; and

maintenance diagnostic means coupled to said maintenance bus for off-line testing of each of said plurality of said central processing modules, each of said plurality of input/output modules, and said memory control units of each of said plurality of memory modules;

2. The data processing system of claim 1 wherein said memory control unit further includes:

means for correcting all single-bit errors in information received from said at least one memory storage unit associated with said memory control unit before said transfer of information to said memory bus.