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Large scale multi-level information processing system employing improved failsaft techniques

  • US 3,905,023 A
  • Filed: 08/15/1973
  • Issued: 09/09/1975
  • Est. Priority Date: 08/15/1973
  • Status: Expired due to Term
First Claim
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1. A multi-processing modular data processing system including a plurality of peripheral devices comprising:

  • a plurality of memory modules interconnected by a memory bus to provide a multi-accessable main memory for said system, each of said plurality of memory modules including a memory control unit and at least one memory storage unit, each of said memory control units being connected to said memory bus and including means for detecting errors in the transfer of information between said memory bus and said memory storage unit;

    a plurality of central processing modules, each of said plurality of central processing modules including a program control section and a storage section, each of said storage sections being connected to said memory bus and including means for indicating malfunctions internal to said respective processing module and errors related to information transfer between said respective processing module and said main memory;

    a plurality of input/output modules, each of said input/output modules including a memory interface unit and a translator unit, said memory interface unit of each of said plurality of input/output modules being connected to said memory bus, said translator unit of each of said plurality of input/output modules being connected to said program control section of each of said processing modules for receiving control information and including means for detecting and reporting malfunctions internal to said respective input/output module and errors related to information transfers between said respective input/output module and said plurality of peripheral devices;

    a maintenance bus coupled to each of said memory control units of said plurality of memory modules and to each of said storage sections of said plurality of central processing modules and to each of said memory interface units of said plurality of input/output modules; and

    maintenance diagnostic means coupled to said maintenance bus for off-line testing of each of said plurality of said central processing modules, each of said plurality of input/output modules, and said memory control units of each of said plurality of memory modules;

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