Direct digital logarithmic encoder

• US 3,905,028 A
• Filed: 08/02/1973
• Issued: 09/09/1975
• Est. Priority Date: 08/02/1973
• Status: Expired due to Term

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Ching-Long Song, John R. Sergo Jr, Paul A. Wintz
• Inventors: Wintz, Paul A., Sergo, John R. Jr., Song, Ching-Long
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/385,095
• Time in Patent Office: 768 Days
• Field of Search: 340/347AD 179/15AV 325/38B
• US Class Current: 341/138
• CPC Class Codes: H03M 1/48 Servo-type converters

Abstract

An analog-to-digital converter is disclosed which directly converts analog signals, such as voice, into digital signals exhibiting logarithmic compression characteristics. The apparatus is digitally controlled, performs encoding at minimal operating speed and may be utilized on a per line basis.

Claims

1. In an apparatus for continuously tracking and digitally encoding a variable analog input signal according to a logarithmic encoding scheme in which a plurality of chords, each having a plurality of steps is defined, input means over which said analog input signal is received, reference means for providing a predetermined reference signal, comparator means connected to said input means and said reference means for providing output signals indicating the difference in the relative value of said reference signal and said variable analog input signal, second means including a reversible counter means responsive to said output signals to selectively advance and decrease to provide a set of code signals which represent the step number, the chord number, and at least the sign of the chord number, signal processing means including a chord identifier circuit and a digital to analog converter operative to provide feedback signals of different values in response to the receipt of said code signals which represent different ones of said chord numbers and said output signal, the amplitude of which varies for different chords, each step in a chord having the same fixed ampLitude, and means in said reference means for summing the signals output from said signal processing means with said predetermined cumulative reference signal to thereby continuously provide a modified reference signal to said first means to allow for continuous tracking and digital encoding of said variable analog input signal according to a logarithmic encoding scheme, and output means for deriving encoded digital signals from said reversible counter means at periodic intervals.

2. An apparatus as set forth in claim 1 in which said comparator means includes control means for gating the signal output of said comparator means to said reversible counter means at periodic intervals.

3. An apparatus as set forth in claim 1 in which the signal output from said comparator means controls said counter means to find and track the level of the analog signal and to provide a binary count which represents the same.

4. An apparatus as set forth in claim 3 in which said counter has a plurality of bit positions for representing the level of said analog signal including a first set of bit positions assigned to represent the step number;

a second set of bit positions assigned to represent the chord number; and

a third set assigned to represent at least the sign of the chord, and which includes means for outputting the information in said counter.

5. An apparatus as set forth in claim 1 in which said output signals of said signal processing means vary logarithmically according to the chord being transversed.

6. In an apparatus for continuously tracking and digitally encoding a variable analog input signal according to a logarithmic encoding scheme in which a plurality of chords, each having a plurality of steps is defined;

input means over which said variable analog signal is received, reference means for providing a predetermined reference signal, comparator means connected to said input means and said reference means for providing output signals indicating the relative value of said reference signal and said analog signal, reversible counter means incremented and decremented by said output signals at predetermined intervals to provide a set of code signals which represent the step number, the chord number, and at least the sign of the chord number, signal processing means including a decoder circuit and digital to analog converter means operative to provide signals of different values in response to the receipt of the code signals which represent different chord numbers, amplification means for amplifying the different value analog signals output from said signal processing means to provide a feedback signal, the amplitude of which varies for different chords, each step in a chord having the same fixed amplitude, third means for modifying the amplifying factor of said amplification means in accordance with said output signals, and means for summing said feedback signal as modified by said amplification means with said predetermined reference signal to thereby continuously provide a cumulative reference signal to said comparator means to allow for continuous tracking and digital encoding of said variable analog input signal according to a logarithmic encoding scheme, and output means for deriving digital encoded signals from said reversible counter means at predetermined intervals.

7. An apparatus as set forth in claim 6 in which said comparator means provides a first signal in response to input of an analog signal which is greater than said reference signal, and a second signal in response to input of an analog signal which is less than said reference signal, and in which said third means is connected to provide said first and second signals to said amplification means to control same to provide an amplification factor of +1 and -1 respectively.

8. An apparatus as set forth in claim 6 in which which includes means for outputting digital signals which represent an encoding of the step and chord numbers contained in said reversible counter means.

9. An apparatus as set forth in claim 6 in which said counter means has a first set of bit positions assigned to represent the step number, a second set of bit positions assigned to represent the chord number, and a third set of bit positions assigned to represent at least the sign of the chord number, and in which said counter means are incremented by said comparator means whenever the analog signal is greater than said reference signal, and decremented by said comparator means whenever said reference signal is greater than said analog signal.

10. An apparatus as set forth in claim 6 in which said counter means provides m chord bits, and in which said signal processing means includes a sign controlled inverter responsive to said m chord bits and the sign signal provided by said second means to convert a negative chord number into the m bit symmetric positive binary equivalent of said negative number, and an m to 2m decoder connected to said inverter for providing one of 2m output signals in response to the m bit binary input from said inverter.

11. An apparatus as set forth in claim 6 in which said comparator means includes a first input connected to said input means and a second input connected to said reference means, and a flip-flop circuit for gating the different levels output from said comparator circuit to said second means.

12. In an apparatus for continuously tracking and digitally encoding a variable analog input signal according to a logarithmic encoding scheme, input means over which said analog signal is received, reference means for providing a predetermined reference signal, comparator means connected to said input means and said reference means operative to provide a first signal whenever the value of said analog signal exceeds the value of said reference signal, and a second signal whenever said analog signal is less in value than said reference signal, reversible counter means having a plurality of bit positions, control means for selectively gating the output of said comparator means to said counter means, said reversible counter means being incremented in response to said first signal and decremented in response to said second signal, a first set of said bit positions being assigned to register code signals representative of the step number, a second set of said bit positions being assigned to register code signals representative of the chord number, and at least one of said bit positions being assigned to register code signals representative of sign of the chord number, digital processing means for generating different signal outputs for different code signal inputs, means for transmitting the code signals in said reversible counter means which represent the chord number of said digital processing means to said digital processing means, D/A converter connected to said digital processing means for generating analog feedback signals having an amplitude which varies for different chords, each step in a chord having the same fixed amplitude, amplification means controlled by the output of said D/A converter means by a first factor whenever said first signal appears at the output of said control means and to amplify the output of said D/A converter means by a second different factor whenever said second signal appears at the output of said control means, and means connected to said amplification means for summing the amplified signals with said predetermined reference signal to thereby track said input analog signals and to continuously provide a modified reference signal to said comparator means to allow for continuous tracking and digital encoding of said variable analog input signal according to a logarithmic encoding scheme, and output means for deriving digital encoded signals from said reversible counter means at predetermined intervals.

13. In an apparatus for continuously tracking and digitally encoding a variable analog input signal according to a 2m chord, 2n step logarithmic encoding scheme;

comparator means for comparing said analog input signal with a predetermined reference signal operative to output a first signal whenever said analog signal exceeds said reference signal, and to output a second signal whenever said analog signal does not exceed said reference signal, an n+m+1 bit reversible counter, the n least significant bits of said reversible counter representing the step number, the next m most significant bits of said reversible counter representing the chord number and the most significant bit of said reversible counter being a sign bit, control means connected to said comparator means for gating the output of said comparator means to said reversible counter, said reversible counter being incremented in response to said first signal and being decremented in response to said second signal, digital processing means connected to said counter operative to receive said m chord number bits from said counter and to energize one of 2m output lines, the energized one of said lines being determined by the binary value of said received bits, analog signal generating means connected to said digital processing means for generating a plurality of analog signal levels, each of said signal levels being associated with and generated in resonse to a predetermined one of said 2m output lines being energized, the amplitude of said signal levels being different for different chords, each step in a chord having the same fixed amplitude, amplification means connected to the output of said control means and to the output of said analog signal generating means for amplifying the output of said signal generating means by a factor of +1 whenever said first signal appears at the output of said control means, and for amplifying the output of said generating means by a factor of -1 whenever said second signal appears at the output of said control means, an integrator connected to said amplification means for summing the amplified signal output therefrom with said predetermined reference signal to thereby continuously provide a modified reference signal for input to said comparator means thus closing the encoding loop, and providing continuous tracking of the input analog signals and a digital encoding thereof according to a logarithmic encoding scheme, and output means for deriving digital encoded signals from said reversible counter at predetermined intervals.

14. An apparatus as set forth in claim 13 which includes reset means for resetting said counter to the code word indicative of the predetermined reference signal and resetting said integrator to output said predetermined reference signal and thereby indicating further finding and tracking of the analog signal.

15. An apparatus as set forth in claim 13, in which said output means includes means for outputting the digital signals in said counter in a parallel pattern, thereby directly extracting from the encoding loop digital signals exhibiting logarithmic encoding characteristics.

16. An apparatus in accordance with claim 13 wherein said control means further comprises a flip-flop for gating said first and second signal levels to said counter, and a clock for periodically enabling both said flip-flop and said counter.

17. An apparatus in accordance with claim 13 in which said counter means provides m chord bits, and in which said digital means further comprises a sign controlled inverter responsive to said m chord bits and the sign signal provided by said counter means to convert a negative chord number into the m bit symmetric positive binary equivalent of said negative number, and an m to 2m decoder connected to said inverter for providing one of 2m output signals in response to the m bit binary number input from said inverter.

18. A method for continuously tracking and digitally encoding a variable analog input signal according to a 2m chord, 2n step, logarithmic encoding scheme, with an apparatus which includes a comparator circuit, a reversible counter, a D/A converter circuit and a summing circuit, comprising the steps of comparing said analog input signal with a predetermined reference signal in a comparator circuit, generating a first signal in said comparator circuit whenever said analog input signal exceeds said reference signal to increment a reversible counter by one step, generating a second signal in said comparator circuit whenever said input signal does not exceed said reference signal to decrement said counter by one step, extracting from said counter the number which corresponds to the chord being traversed, converting said extracted number in a decoder circuit into a unique signal indicative of the chord which is being traversed and generating an analog signal lever with digital to analog means which has an amplitude which varies for different chords, each step in a chord having the same fixed amplitude, modifying the generated analog signal level by different factors for said first and second signals, summing said modified analog signal level with said predetermined reference signal to thereby continuously generate a new reference signal for comparison withh said variable analog input signal, and periodically extracting a digitally encoded signal from said reversible counter which represents said analog input signal according to a logarithmic encoding scheme.

19. A method as set forth in claim 18 which includes the further step of reinitiating the finding and tracking operation by providing said predetermined reference signal in unmodified form and resetting the counter.

20. A method as set forth in claim 18 which includes the further step of extracting the chord step and sign information contained in said counter.

21. A method for continuously tracking and digitally encoding a variable analog input signal according to a 2m chord, 2n step, logarithmic encoding scheme, with an apparatus comprising a comparator circuit, a reversible counter, a D/A converter circuit and a summing circuit, comprising the steps of comparing said analog input signal with a predetermined reference signal in a comparator circuit, generating a first signal in said comparator circuit whenever said analog input signal exceeds said reference signal to increment a 2n step, 2m chord reversible digital counter by one step, generating a second signal in said comparator circuit whenever said input signal does not exceed said reference signal to decrement said counter by one step, extracting from said counter the binary number which corresponds to the chord number being traversed, converting said extracted number in a decoder circuit into a unique signal indicative of which of said 2m chords is being traversed, generating with digital to analog means a different analog signal level for different converted binary numbers, the amplitude of the signal level being different for different chords, each step in a chord having the same fixed amplitude, amplifying the generated analog signal level by a factor of +1 whenever said first signal is input to said counter, and amplifying said generated analog signal level by a factor of -1 whenever said second signal is input to said counter, integrating said amplified analog signal level with said predetermined reference signal, thereby continuously generating a new reference for comparison with said variable analog input signal, and periodically extracting a digitally encoded signal from said reversible counter which represents said analog signal according to a logarithmic encoding scheme.