Care memory control circuit

• US 3,906,453 A
• Filed: 03/27/1974
• Issued: 09/16/1975
• Est. Priority Date: 03/27/1974
• Status: Expired due to Term

• Current Assignee: AST Research, Inc. (Samsung Electronics Co. Ltd.)
• Original Assignee: Bruno A. Mattedi, Jitendra G. Nemivant
• Inventors: Mattedi, Bruno A., Nemivant, Jitendra G.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Vandenburg, John P.
• Application Number:
  US05/455,417
• Time in Patent Office: 538 Days
• Field of Search: 340/172.5,173
• US Class Current: 711/107
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

An interchangeable memory system includes a novel core memory control circuit for rendering a non-volatile magnetic core random access memory having a two-part memory cycle, for sequential reading and writing operations, interchangeable with a simultaneously read and written volatile semiconductor random access memory in a known semiconductor digital data processing system having a time-shared address bus and a time-shared instruction and data bus, the address bus being operable to access program read-only memory and data random access memory locations at alternate time intervals, and the instruction and data bus being operable to alternately carry read-only memory instruction signals and bi-directional random access memory data signals, the latter signals for simultaneous semiconductor random access memory reading and writing operations. The core memory control circuit enables compatible substitution of the sequentially read and written magnetic core random access memory for the simultaneously read and written semiconductor random access memory in the data processing system without circuit modifications to the latter.

Claims

1. In combination with an electronic digital processing system having an addressable program read-only memory, an addressable volatile semiconductor random access memory, central processing means for obtaining and executing program instruction signals from said read-only memory and for retrieving variable transaction output data signals from and simultaneously entering variable transaction input data signals into said semiconductor random access memory, time-shared address bus means for receiving address signals from said processing means to sequentially and repetitively access preselected address locations in said readonly memory And said random access memory during first and second intersticed time intervals, respectively, time-shared instruction and data bus means connected to said processing means and operable to obtain said instruction signals during said second time intervals, and to retrieve said output data signals and enter said input data signals during said first time intervals, both said address bus means and said instruction and data bus means being cleared of signals during the time intervals between said first and second time intervals, and write command means connecting said processing means with said random access memory for providing write command signals to the latter to enter said input data signals therein during certain of said first time intervals in accordance with said instruction signals;

wherein the improvement comprises core memory control circuit means for compatibly connecting said address bus means, said instruction and data bus means and said write command means with a nonvolatile magnetic core random access memory having repetitive memory cycles each initiated after a said second time interval and comprising first and second parts, output data signals being retrieved from said core memory during said first parts and input data signals being entered into said core memory during said second parts, said core memory control circuit means comprising;

memory cycle timing signal means for repetitively initiating each said memory cycle and sequentially determining said first and second parts thereof, core memory write signal means for controlling said core memory to enter said input data signals therein during certain of said second parts in response to said write command signals, address latching means for stabilizing prior to each said first part said random access memory address signals received from said address bus means during the said second time interval next preceding said first part, data latching means for stabilizing prior to each said second part said input data signals received from said instruction and data bus means during the said first time interval next preceding said second part, and data output means for presenting at the output thereof said output data signals retrieved from said core memory said instruction and data bus means during each said first time interval and for floating said output during each said second time interval, whereby said core memory control circuit means renders said sequentially read and written magnetic core random access memory interchangeable with said simultaneously read and written semiconductor random access memory.

2. The core memory control circuit means of claim 1, wherein said processing system is controlled for time-shared operation of said bus means by first and second synchronized and phased clock signals, said second signal being of twice the frequency of said first signal;

two monostable multivibrators, said memory cycle timing signal means providing signals derived from both said clock signals to control said multivibrators to provide timing pulse signals at the beginnings of said first and second parts of said memory cycles.

3. The core memory control circuit means of claim 1, wherein said processing system is controlled for time-shared operation of said bus means by first and second synchronized and phased clock signals, said second signal being of twice the frequency of said first signal;

said address latching means comprising an electronic latch for said address signals controlled by a signal derived from said first clock signal.

4. The core memory control circuit means of claim 1, wherein said processing system is controlled for time-shared operation of said bus means by first and second synchronized and phased clock signals, said second signal being of twice the frequency of said first signal;

said data latching means comprising an electronic latch for said input data signals controlled by a signal derived from said first clock signal.

5. The core memory control circuit means of claim 1, wherein saId central processing unit is operable to select input-output circuits instead of said semiconductor random access memory for interchange of data signals during certain of said first time intervals in accordance with said instruction signals, said write command means being additionally operable to provide an input-output selection signal during the said second time interval next preceding each of said certain first time intervals, and wherein said processing system is controlled for time-shared operation of said bus means by first and second synchronized and phased clock signals, said second signal being of twice the frequency of said first signal;

said core memory write signal means comprising first and second electronic latches controlled by signals derived from said first clock signal and said write command signals, said first latch being operable to provide memory cycle disable signals in response to said input-output selection signals, and said second latch being operable to provide write signals to said core memory during said certain second parts in response to said write command signals.

6. The core memory control circuit means of claim 5, wherein said data output means comprises first gating means for gating said output data signals retrieved from said core memory with a strobe signal produced during each said first time interval by an electronic latch controlled by signals derived from said clock signals, and second gating means for gating the output of said first gating means with said memory cycle disable signals for floating said output of said data output means during each memory cycle during which input-output selection occurs.

7. The core memory control circuit means of claim 6, wherein said second gating means are drivingly coupled to the gates of metal oxide semiconductor field-effect transistors, the output terminals of said transistors being connected to said instruction and data bus means.