Decoder input circuit for receiving asynchronous data bit streams

• US 3,906,484 A
• Filed: 09/13/1972
• Issued: 09/16/1975
• Est. Priority Date: 09/13/1972
• Status: Expired due to Term

• Current Assignee: ABB Power T&D Limited (ABB Limited)
• Original Assignee: George W. Lipscomb, Waymon A. Melvin Jr
• Inventors: Melvin, Waymon A. Jr., Lipscomb, George W.
• Primary Examiner(s): Morrison, Malcolm A.
• Application Number:
  US05/288,863
• Time in Patent Office: 1,098 Days
• Field of Search: 340/347DD 179/15BA,15BS 178/69.5R
• US Class Current: 375/370
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20

Abstract

A decoder input circuit has a continuous mode of operation to receive an asynchronous data bit stream having isochronous data bits. An internal clocking arrangement is synchronized with the start bit of each of a continuous series of data words included in the stream. Each data word bit is clocked into a temporary storage register for readout to a decoder. The storage register is cleared at the end of each data word and the cycle is repeated as a start bit logic is received following the end bit logic. When a start bit logic is not received, the storage register continues to be loaded with the number of data bit intervals included in each data word so that the input circuit is recycled for resynchronizing with the next following start bit. The input circuit is maintained in coincident operation in the event that a start bit is missed.

Claims

1. A decoder input including a data receiving circuit for maintaining synchronism with continuously received binary encoded data including regularly occurring start and end of word information subject to random omissions of said start information, said data receiving circuit, comprising:

data input means receiving an isochronous data bit stream characterized by a continuous series of binary coded data words having a common N number of data bits including start and end bits of first and second binary states, respectively, and wherein the interval of each data bit is subject to small variations relative to a predetermined data bit interval;

internal clock means continuously generating multiphase clock pulses in a predetermined order including first, second and third phase clock pulses consecutively occurring during an interval substantially equal to said predetermined data bit interval, and wherein said multiphase clock pulses have commonly adjustable phase relationships relative to each interval;

storage register means recurrently entering each of N data bit intervals occurring at said data input means under shifting control of said second phase clock pulses;

pulse counter means responsive to said second phase clock pulses and recurrently counting from a first count to an N number count of said second phase clock pulses;

logic control circuit means firstly responsive to said third phase clock pulses when coincident with said N number count of said pulse counter means and secondly responsive to said first phase clock pulses when coincident with a first count of said pulse counter means;

enabling circuit means developing an enabling pulse controlled by said logic control circuit means such that said enabling pulse extends between the consecutive occurrences of said firstly and secondly named responses of said logic control circuit means; and

synchronizing circuit means generating a synchronizing pulse effective to coincidently adjust the phase relationships of said multiphase clock pulses in response to the transition from the second to the first binary state at said data input means when the last named transition is coincident with said enabling pulse such that the interval of each of said start data bits is synchronized with a second phase clock pulse at said storage register means and upon absence of one of said start bits the data word associated therewith is entered into said storage register in synchronism with the last previous data word containing a start data bit.

2. The decoder input including a data receiving circuit as claimed in claim 1 wherein said first, second, and third phase clock pulses have substantially equal time spaced relationships between the ends of each data bit interval such that said enabling pulse enables said synchronizing circuit means to initiate said synchronizing pulse for substantially one-half of said predetermined data bit interval during the end and start data bit intervals of consecutive data words.

3. The decoder input including a data receiving circuit as claimed in claim 2 including means generating a flag signal in response to said third phase clock pulse occurring during the end data bit interval of each data word such that said flag signal indicates receipt of N data bit intervals at the storage register means.

4. The decoder input including a data receiving circuit as claimed in Claim 3 wherein the synchronizing circuit means includes a one-shot multivibrator circuit for producing a pulse in response to the transition from the second to the first binary state, and further includes a gating circuit means connected to said one-shot multivibrator circuit, the enabling circuit means, and the data input means for being initially enabled by the coincidence of the enabling pulse and the first binary state of the data bit stream at said data input means to produce the synchronizing pulse in response to the multivibrator pulse.

5. The decoder input including a data receiving circuit as claimed in claim 2 including start circuit means responsive to an external set control signal to operate the data receiving circuit from an inactive operative state wherein said data receiving circuit is inhibited from processing the data bits to said storage register to a standby active operative state wherein said data receiving circuit is enabled for initially receiving and accumulating data words prior to receiving said data bit stream being applied to said data input means whereupon said data receiving circuit is rendered to a data processing active operative state.

6. The decoder input including a data receiving circuit as claimed in claim 5 including a false start logic circuit means responsive to the coincidence of the occurrence of a second binary state at said data input means immediately following an initial momentary occurrence of a first binary state for less than substantially one half of said predetermined data bit interval and, upon the beginning of the occurrence of a second phase clock pulse so as to signal said start circuit means to render said data receiving circuit into said inactive operative state following the false start condition due to the first binary state signal which returns to said second binary state before said one second phase clock pulse occurs, and further wherein said false start logic circuit means returns said data receiving circuit to the standby active operative state at the end of said second phase clock pulse thereby conditioning the receiving circuit for initially receiving a first data word of a bit stream.

7. The decoder input including a data receiving circuit as claimed in claim 6 including further circuit means responsive to the third phase clock pulse occurring during an end data bit interval and further including switch means for selectively connecting and disconnecting said further circuit means to said start circuit means so that when said switch means connects said further circuit means to said start control circuit said further circuit means is effective in response to said last named third phase clock pulse to momentarily render said data receiving circuit to the inactive operative state and thereafter return the data receiving circuit to the standby active operative state, whereby, a bit stream including asynchronous data with an end data bit having a duration longer than a single data bit interval is receivable by said data receiving circuit so as to be enabled to said data processing active operative state.

8. The decoder input including a data receiving circuit as claimed in claim 6 wherein said predetermined data bit intervals of said bit stream have a sixty Hertz frequency rate.

9. The decoder input including a data receiving circuit as claimed in claim 8 wherein N is equal to 16.