Access control assembly

• US 3,911,397 A
• Filed: 05/09/1974
• Issued: 10/07/1975
• Est. Priority Date: 10/24/1972
• Status: Expired due to Term

• Current Assignee: Charles C. Freeny, Jr. (Freeny)
• Original Assignee: Charles C. Freeny, Jr. (Freeny)
• Inventors: Freeny, Charles C. Jr.
• Primary Examiner(s): Yusko, Donald L.
• Application Number:
  US05/468,486
• Time in Patent Office: 516 Days
• Field of Search: 340/147MD,149R,149A,152T,164R
• US Class Current: 340/5.25
• CPC Class Codes: G07C 2009/00468 after n uses
• CPC Class Codes: G07C 2009/00761 with data transmission performed by connected means, e.g. mechanical contacts, plugs, connectors
• CPC Class Codes: G07C 2009/00865 remotely by wireless communication
• CPC Class Codes: G07C 2009/0088 centrally
• CPC Class Codes: G07C 9/00309 operated with bidirectional data transmission between data carrier and locks
• CPC Class Codes: G07C 9/00857 where the code of the data carrier can be programmed
• CPC Class Codes: G07F 7/0866 by active credit-cards adapted therefor G07F7/1008 takes precedence

Abstract

An improved access control assembly including a key assembly constructed to receive a time division binary key code from a remotely located encoder station in the code receive mode of operation, and a lock assembly constructed to control access to a secured device or a secured area, the lock assembly having a predetermined time division binary lock code encoded therein uniquely identifying the lock assembly. When the key assembly is connected to the lock assembly, a time division binary lock recognition code, having a predetermined code format, is generated by the lock assembly and received by the key assembly, the key assembly generating the key code in response to the received lock recognition code detected by the key assembly to have the proper, predetermined code format. The key code generated by the key assembly is received by the lock assembly and compared with the lock code, the lock assembly operating to provide access to the secured device or the secured area in response to a received key code identical to the lock code. The lock assembly generates a signal in response to a comparison indicating the received key code differs from the lock code or in response to the operation of the lock assembly to provide access to the secured device or the secured area which is received by the key assembly and causes the key assembly to destroy the previously received key code and conditions the key assembly in the code receive mode for receiving subsequent key codes from the encoder station.

Claims

1. An access control apparatus, comprising:

a data synchronization assembly generating an output clock signal;

a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising;

a key code storage unit having a portion storing a predetermined time division binary key code in the code storage mode, the key code storage unit having a portion for receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and

a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly, the lock assembly comprising;

a lock decoder and comparator assembly having a portion for receiving the key code clocked from the key code storage unit and for receiving the data synchronization assembly clock signal, the received clock signal clocking the received key code into the lock decoder and comparator assembly, a portion of the lock decoder and comparator assembly having a predetermined time division binary lock code encoded therein, and a portion of the lock decoder and comparator assembly comparing the received key code with the lock code and providing one output signal in response to an identical comparison of the received key code and the lock code and providing the output signal for clearing the key code from the key code storage unit in response to a difference between the compared key code and lock code, the lock decoder and comparator assembly comprising;

a decoder shift register receiving the key code from the key code storage unit and the data synchronizatIon assembly clock signal, the received key code being clocked into the decoder shift register via the received clock signal;

a lock code generator having the lock code encoded therein and a portion receiving the clock signal generated via the data synchronizaton assembly, the lock code generator providing the lock code via an output signal in response to a received clock signal;

means receiving the key code from the key code storage unit and the lock code from the lock code generator, comparing the received lock code and the received key code, and providing the lock decoder and comparator assembly output signal indicating a difference between the lock code and the key code for clearing the key code from the key code storage unit;

a format decoder receiving the key code clocked into the decoder shift register and providing an output signal in response to a received key code having a predetermined code format clocked into the decoder shift register; and

means receiving the format decoder output signal and the data synchronization assembly clock signal, said means providing the clock signal to the lock code generator in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the decoder shift register.

2. The apparatus of claim 1 defined further to include:

means having a portion for receiving the output signal indicating an identical comparison between the lock code and the key code and receiving the format decoder output signal, said means providing the output signal for clearing the key code stored in the key assembly in response to the received signal indicating an identical comparison between the key code and the lock code and providing the output signal for clearing the key code stored in the key assembly in response to a received key code having a predetermined code format; and

wherein the key code storage unit is defined further to include a portion for receiving the lock decoder and comparator assembly output signal indicating an identical comparison between the key code and the lock code and clearing the stored key code in response thereto, and for receiving the lock decoder and comparator output signal indicating a received key code having a predetermined code format and clearing the stored key code in response thereto.

3. The apparatus of claim 2 wherein the key assembly is defined further to include:

a data synchronization assembly generating an output clock signal; and

wherein the lock assembly is defined further include;

a lock recognition code generator having a predetermined lock recognition code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock recognition code generator providing the lock recognition code via an output signal in response to a received clock signal; and

wherein the key assembly is defined further to include;

a key decoder assembly receiving the lock recognition code generator output signal and the data synchronization assembly output clock signal, the key decoder assembly providing an output signal for conditioning the key code storage unit in the code transmission mode in response to a received lock recognition code having a predetermined code format; and

wherein the key code storage unit includes a portion receiving the key decoder assembly output signal and conditioning the key code storage unit in the code transmission mode in response to a received key decoder output signal indicating a received lock recognition code having a predetermined code format.

4. An access control apparatus, comprising:

a key assembly, comprising;

a data synchronization assembly generating an output clock signal;

a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assemblY encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising;

a key code storage unit, a portion for receiving time division binary key codes and the data synchronization assembly clock signal in a code receive mode and a portion storing one of the received key codes in the code storage mode, the key code storage unit having a portion receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal, and the key code storage unit including a portion receiving a signal for conditioning the key code storage unit in the code receive mode in one state of the received signal and for conditioning the key code storage unit in the code transmission mode in one other state of the received signal, the key code storage unit being conditioned in the code receive mode in response to the received signal in the one state of the received signal and the key code storage unit being conditioned in the code transmission mode in response to the received signal in the one other state of the received signal;

a key decoder assembly, comprising;

a decoder shift register having a portion for receiving a time division binary lock recognition code and the data synchronization assembly clock signal, the lock recognition code being clocked into the decoder shift register when receiving the data synchronization assembly clock signal and the lock recognition code;

a format decoder having a portion for receiving the lock recognition code clocked into the decoder shift register and providing an output signal indicating a lock recognition code having a predetermined code format clocked into the decoder shift register; and

means having a portion for receiving the format decoder output signal indicating a lock recognition code having a predetermined code format clocked into the decoder shift register and providing the output signal in the one state for conditioning the key code storage unit in the code transmission mode in response thereto, the key code storage unit receiving the output signal for conditioning the key code storage unit in the code transmission mode and the key code storage unit being conditioned in the code transmission mode in response thereto, said means having a portion for receiving a signal and changing the state of said means output signal to the one other state for conditioning the key code storage unit in the code receive mode in response thereto, the key code storage unit receiving the output signal for conditioning the key code storage unit in the code receive mode in response thereto and the key code storage unit being conditioned in the code receive mode in response thereto; and

a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly, the lock assembly comprising;

a lock decoder and comparator assembly having a portion for receiving the key code from the key code storage unit and providing an output signal in response to the received key code for clearing the stored key code from the key code storage unit, the lock decoder and comparator output signal being received by the means in the key assembly providing the output sIgnal for conditioning the key code storage unit in the code receive mode in one state of said means output signal and for conditioning the key code storage unit in the code transmission mode in one other state of said means output signal and the state of said means output signal being changed to provide an output signal for conditioning the key code storage unit in the code receive mode in response to receiving the lock decoder and comparator assembly output signal;

a lock recognition code generator having a portion storing the predetermined time division binary lock recognition code therein and a portion for receiving the data synchronization assembly clock signal, the lock recognition code being clocked from the lock recognition code generator in response to receiving the data synchronization assembly output signal thereby providing the lock recognition code generator output signal having the lock recognition code encoded therein, the lock recognition code clocked from the lock recognition code generator being received by the decoder shift register in the key assembly.

5. An access control apparatus, comprising:

a data synchronization assembly generating an output clock signal;

a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising;

a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom;

a key code storage unit having a portion for receiving time division binary key codes via the key receiver output signal and for receiving the data synchronization assembly clock signal in a code receive mode of the key code storage unit and storing one of the received key codes in a portion thereof in the code storage mode of the key code storage unit, the key code storage unit receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal, the key code storage unit comprising;

a key code storage shift register, having a portion receiving the time division binary key codes and the data synchronization assembly clock signal, the received key codes being clocked into the key code shift register in the code receive mode;

means conditioning the key code storage unit in the code storage mode in response to a received key code clocked into the key code storage shift register having a predetermined code format;

means conditioning the key code storage unit in the code transmission mode for generating and providing the key code stored in the key code storage unit via the key code storage unit output signal; and

means receiving the key codes from the key receiver assembly and the data synchronization assembly clock signal, said means connecting the received key codes and the clock signal to the key code storage shift register and conditioning the key code storage unit in the code receive mode; and

a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in respoNse to a key code received from the key assembly, the lock assembly comprising;

a lock decoder and comparator assembly having a portion for receiving the key code from the key code storage unit and providing an output signal in response to the received key code for clearing the key code from the key code storage unit, the lock decoder and comparator assembly output signal being received by the key code storage unit and the key code stored in the key code storage unit being cleared from the key code storage unit in response thereto.

6. An access control apparatus, comprising:

a data synchronization assembly generating an output clock signal;

a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising;

a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom;

a key code storage unit having a portion for receiving time division binary key codes via the key receiver assembly output signal and for receiving the data synchronization assembly clock signal in a code receive mode of the key code storage unit and storing one of the received key codes in a portion thereof in the code storage mode of the key code storage unit, the key code storage unit receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal, the key code storage unit comprising;

a key code storage shift register having a portion for receiving time division binary key codes and the data synchronization assembly output clock signal, the received key codes being clocked into the key code storage shift register in the code receive mode;

a format decoder having a portion for receiving the key code clocked into the key code storage shift register and providing an output signal indicating a key code having a predetermined code format clocked into the key code storage shift register;

means having a portion for receiving the format decoder output signal and providing an output signal in the high state in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the key code storage shift register;

an inverter receiving the output signal provided in response to the format decoder output signal and providing an inverted output signal in response thereto, the inverter output signal being in the high state when receiving a signal in the low state and being in the low state when receiving a signal in the high state;

an AND gate receiving the inverter output signal and the key codes via the key receiver assembly output signal and providing the received key codes via the AND gate output signal in the high state of the inverter output signal, the AND gate being inoperative in the low state of the inverter output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; and

an OR gate receiving the key codes via the AND gate output signal and receiving the key code storage shift register output signal, the OR gate providing the key codes clocked from the key code storage shift register via the OR gate output siGnal in the code transmission mode and providing the key codes provided via the received AND gate output signal via the OR gate output signal in the code receive mode, the OR gate output signal and the data synchronization assembly clock signal being received by the key code shift register, the key codes received by the key receiver assembly being received via the OR gate and provided via the OR gate output signal and clocked into the key code storage shift register in the code receive mode, and the key code clocked from the key code storage shift register being received by the OR gate and provided via the OR gate output signal and clocked back into the key code storage shift register thereby cyclically providing the key code stored in the key code storage shift register via the key code storage shift register output signal in the code transmission mode; and

a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly.

7. The apparatus of claim 6 wherein the key code storage unit is defined further to include:

an AND gate receiving the data synchronization assembly output clock signal and the output signal provided in response to the format decoder output signal and providing the received clock signal via the AND gate output signal in the high state of the received output signal provided in response to the format decoder output signal in the code transmission mode;

an AND gate receiving the data synchronization assembly output clock signal and the inverter output signal and providing the received clock signal via the AND gate output signal in the high state of the inverter output signal in the code receive mode; and

an OR gate receiving the clock signal via the AND gate output signal provided in the code receive mode and providing the clock signal via the OR gate output signal when receiving the clock signal via one of the received output signals from the AND gates, the OR gate output signal being received via the key code storage shift register providing the clock signal in the code transmission mode and the code receive mode.

8. The apparatus of claim 7 wherein the lock assembly is defined further to include:

a lock recognition code generator having a predetermined lock recognition code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock recognition code generator providing the lock recognition code via an output signal in response to a received clock signal; and

wherein the key assembly is defined further to include;

a key decoder assembly receiving the lock recognition code generator output signal and the data synchronization assembly output clock signal, the key decoder assembly providing an output signal for conditioning the key code storage unit in the code transmission mode in response to a received lock recognition code having a predetermined code format; and

wherein the key code storage unit is defined further to include;

an AND gate receiving the data synchronization assembly output clock signal and the key decoder assembly output signal and providing the clock signal via the AND gate output signal in a high state of the key decoder output signal indicating a received lock recognition code having a predetermined code format, the clock signal provided via the AND gate output signal in response to a received key decoder assembly output signal in the high state being received via the AND gate providing the clock signal in the code transmission mode.

9. The apparatus of claim 8 wherein the key code storage unit is defined further to include:

an AND gate receiving the output signAl provided in response to the format decoder output signal and the key decoder assembly output signal and providing an output signal in the high state in response to the received key decoder assembly output signal in the high state and the received output signal provided in response to the format decoder output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format; and

an AND gate receiving the key code storage shift register output signal and the AND gate output signal provided in response to the received key decoder assembly output signal and the received output signal provided in response to the format decoder output signal, and providing the key code storage shift register via the output signal therefrom when receiving the AND gate output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format, the key code storage shift register output signal provided via the AND gate output signal being received via the OR gate providing the key codes via the OR gate output signal in the code receive mode and in the code transmission mode.

10. An access control apparatus, comprising:

a data synchronization assembly generating an output clock signal;

a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising;

a key code storage unit having a portion for storing a predetermined time division binary key code in the code storage mode, the key code storage unit having a portion for receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and

a key housing structurally supporting the key code storage unit and the data synchronization assembly having a key connector formed on a portion thereof; and

a lock assembly having a portion receiving the key code from the key assembly and providing an output signal in response to receiving a key code from the key assembly for clearing the key code stored in the key assembly, the key code stored in the key assembly being cleared via the lock assembly output signal provided in response to a key code received from the key assembly, the lock assembly comprising;

a lock decoder and comparator assembly having a portion for receiving the key code clocked from the key code storage unit and receiving the data synchronization assembly clock signal, the received clock signal clocking the received key code into the lock decoder and comparator assembly, the lock decoder and comparator assembly having a portion storing a predetermined time division binary lock code therein and a portion comparing the received key code with the lock code and providing one output signal in response to an identical comparison of the received key code and the lock code and providing the output signal for clearing the key code from the key code storage unit in response to a difference between the compared key code and lock code; and

a lock housing structurally supporting the lock decoder and comparator assembly having a lOck connector formed on a portion thereof, the lock connector being connectable to the key connector, the key code storage unit output signal being connected to the lock decoder and comparator assembly via the connection between the lock connector and the key connector, the data synchronization assembly output clock signal being connected to the lock decoder and comparator assembly via the connection between the key connector and the lock connector, and the lock decoder and comparator output signal being connected to the key code storage unit via the connection between the key connector and the lock connector.

11. The apparatus of claim 10 wherein the key assembly includes:

a key power supply connected to the key code storage unit and the data synchronization assembly and providing electrical operating power therefor when connected thereto, the key power supply being connected to the lock decoder and comparator assembly and providing the electrical operating power therefor via the connection between the lock connector and the key connector.

12. An access control apparatus, comprising:

a key assembly, having a portion storing a predetermined time division binary key code in a code storage mode, a portion of the key assembly generating and providing an output signal having the key code stored in the key assembly encoded therein in a code transmission mode thereof, the key assembly having a portion receiving a signal and clearing the key code stored in the key assembly in response thereto, the key assembly comprising;

a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom;

a key code storage unit having a portion for receiving time division binary key codes via the key receiver output signal and receiving the data synchronization assembly clock signal in a code receive mode and a portion for storing one of the received key codes in a portion thereof in the code storage mode, the key code storage unit receiving the data synchronization assembly clock signal and the key code stored in the key code storage unit being clocked therefrom in response to the received data synchronization assembly clock signal thereby providing a key code storage unit output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and

a lock assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion for providing an output signal in response to the received key code storage unit output signal, the lock assembly output signal provided in response to receiving the key code storage unit output signal being received by the key code storage unit and the key code stored in the key code storage unit being cleared in response to receiving the lock assembly output signal provided in response to the received key code storage unit output signal.

13. The apparatus of claim 12 wherein the key receiver assembly is defined further to include:

a receiver speaker receiving key codes via an acoustical data link; and

means receiving the key codes via a direct wire data link.

14. An access control apparatus, comprising:

a key assembly, comprising;

a data synchronization assembly generating an output clock signal;

a key code storage unit, having a code receive mode, and a portion for receiving the clock signal generated via the data synchronization assembly, the key code storage unit having a portion for receiving time division binary key codes in the code receive mode, the key code storage unit having a portion for storing one of the received key codes in the code storage mode, and the key code storage unit having a portion for generating an output signal having the keY code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit comprising;

a key receiver assembly receiving time division binary key codes and providing the time division binary key codes via an output signal therefrom;

a key code storage shift register receiving the key codes via the key receiver assembly output signal and the data synchronization assembly clock signal and the received key codes being clocked into the key code storage shift register in the code receive mode, at least one of the received key codes being stored in the key code storage shift register in the code storage mode, and the key code storage shift register receiving the data synchronization assembly clock signal and the key code stored in the key code storage shift register being clocked from the key code storage shift register in the code transmission mode;

a format decoder having a portion for receiving the key code clocked into the key code storage shift register and providing an output signal indicating a key code having a predetermined code format clocked into the key code storage shift register;

means having a portion for receiving the format decoder output signal and providing an output signal in the high state in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the key code storage shift register;

an inverter receiving the output signal provided in response to the format decoder output signal and providing an inverted output signal in response thereto, the inverter output signal being in the high state when receiving a signal in the low state and being in the low state when receiving a signal in the high state;

an AND gate receiving the inverter output signal and the key codes via the key receiver assembly output signal and providing the received key codes via the AND gate output signal in the high state of the inverter output signal, the AND gate being inoperative in the low state of the inverter output signal indicating a key code having a predetermined code format clocked into the key storage shift register; and

an OR gate receiving the key codes via the AND gate output signal and receiving the key code storage shift register output signal, the OR gate providing the key codes clocked from the key code storage shift register via the OR gate output signal in the code transmission mode and providing the key codes provided via the received AND gate output signal via the OR gate output signal in the code receive mode, the OR gate output signal and the data synchronization assembly clock signal being received by the key code shift register, the key codes received via the key receiver assembly being received via the OR gate and provided via the OR gate output signal and clocked into the key code storage shift register in the code receive mode, and the key code clocked from the key code storage shift register being received via the OR gate and provided via the OR gate output signal and clocked back into the key code storage shift register thereby cyclically providing the key code stored in the key code storage shift register via the key code storage shift register output signal in the code transmission mode; and

a lock assembly, comprising;

a lock decoder and comparator assembly having a portion for receiving the key code generated via the key assembly in the code transmission mode and providing an output signal in response to a received key code; and

a lock control assembly, having a locked position, an unlocked position and a portion receiving the lock decoder and comparator assembly output signal and positioning the lock control assembly in the unlocked position in response thereto.

15. The apparatus of claim 14 wherein the key code storage unit is defined further to include:

an AND gate receiving the data synchronization assembly output clock signal and the output signal pRovided in response to the format decoder output signal and providing the received clock signal via the AND gate output signal in the high state of the received output signal provided in response to the format decoder output signal in the code transmission mode;

an AND gate receiving the data synchronization assembly output clock signal and the inverter output signal and providing the received clock signal via the AND gate output signal in the high state of the inverter output signal in the code receive mode; and

an OR gate receiving the clock signal via the AND gate output signal provided in the code receive mode and providing the clock signal via the OR gate output signal when receiving the clock signal via one of the received output signals from the AND gates, the OR gate output signal being received via the key code storage shift register providing the clock signal in the code transmission mode and the code receive mode.

16. The apparatus of claim 15 wherein the lock assembly is defined further to include:

a lock recognition code generator having a predetermined lock recognition code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock recognition code generator providing the lock recognition code via an output signal in response to a received clock signal; and

wherein the key assembly is defined further to include;

a key decoder assembly receiving the lock recognition code generator output signal and the data synchronization assembly output clock signal, the key decoder assembly providing an output signal for conditioning the key code storage unit in the code transmission mode in response to a received lock recognition code having a predetermined code format; and

wherein the key code storage unit is defined further to include;

an AND gate receiving the data synchronization assembly output clock signal and the key decoder assembly output signal and providing the clock signal via the AND gate output signal in a high state of the key decoder output signal indicating a received lock recognition code having a predetermined code format, the clock signal provided via the AND gate output signal in response to a received key decoder assembly output signal in the high state being received via the AND gate providing the clock signal in the code transmission mode.

17. The apparatus of claim 16 wherein the key code storage unit is defined further to include:

an AND gate receiving the output signal provided in response to the format decoder output signal and the key decoder assembly output signal and providing an output signal in the high state in response to the received key decoder assembly output signal in the high state and the received output signal provided in response to the format decoder output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format; and

an AND gate receiving the key code storage shift register output signal and the AND gate output signal provided in response to the received key decoder assembly output signal and the received output signal provided in response to the format decoder output signal, and providing the key code storage shift register via the output signal therefrom when receiving the AND gate output signal in the high state indicating a received lock recognition code having a predetermined code format and a key code in the key code storage shift register having a predetermined code format, the key code storage shift register output signal provided via the AND gate output signal being received via the OR gate providing the key codes via the OR gate output signal in the code receive mode and in the code transmission mode.

18. A key apparatus, comprising:

a data synchronization assembly generating an output clock signal;

a key code stoRage shift register having a portion for receiving time division binary key codes and the data synchronization assembly clock signal and the received key codes being clocked into the key code storage shift register in a code receive mode, a portion of the key code storage shift register storing at least one of the received key codes in a code storage mode, and the key code storage shift register having a portion for receiving the data synchronization assembly clock signal and the key code stored in the key code storage shift register being clocked from the key code storage shift register in a code transmission mode;

a key receiver assembly having a portion for receiving time division binary key codes and providing an output signal corresponding to the received key codes, the key receiver assembly output signal being received by the key code storage shift register in the code receive mode of the key code storage shift register;

a format decoder connected to the key code storage shift register and receiving the key code clocked into the key code storage shift register and providing an output signal indicating a key code having a predetermined code format clocked into the key code storage shift register;

means having a portion for receiving the format decoder output signal and providing an output signal in the high state in response to a received format decoder output signal indicating a key code having a predetermined code format clocked into the key code storage shift register;

an inverter receiving the output signal provided in response to the format decoder output signal and providing an inverted output signal in response thereto, the inverter output signal being in the high state when receiving a signal in the low state and being in the low state when receiving a signal in the high state;

an AND gate receiving the inverter output signal and the key codes via the key receiver assembly output signal and providing the received key codes via the AND gate output signal in the high state of the inverter output signal, the AND gate being inoperative in the low state of the inverter output signal indicating a key code having a predetermined code format clocked into the key code storage shift register; and

an OR gate receiving the key codes via the AND gate output signal and receiving the key code storage shift register output signal, the OR gate providing the key codes clocked from the key code storage shift register via the OR gate output signal in the code transmission mode and providing the key codes provided via the received AND gate output signal via the OR gate output signal in the code receive mode; and

wherein the key code storage shift register receives the OR gate output signal and the data synchronization assembly clock signal, the key codes received via the key receiver assembly being received via the OR gate output signal and clocked into the key code storage shift register in the code receive mode, and the key code clocked from the key code storage shift register being received via the OR gate output signal and clocked back into the key code storage shift register thereby cyclically providing the key code stored in the key code storage shift register via the key code storage shift register output signal in the code transmission mode.

19. The apparatus of claim 18 wherein the key code storage unit is defined further to include an AND gate receiving the data synchronization assembly output clock signal and the output signal provided in response to the format decoder output signal and providing the received clock signal via the AND gate output signal in the high state of the received output signal provided in response to the format decoder output signal in the code transmission mode;

an AND gate receiving the data synchronization assembly output clock signal and the inverter output signal and providing the received clock signal via the AND gate output signal in the high state of the inverTer output signal in the code receive mode; and

an OR gate receiving the clock signal via the AND gate output signal provided in the code receive mode and providing the clock signal via the OR gate output signal when receiving the clock signal via one of the received output signal from the AND gates, the OR gate output signal being received via the key code storage shift register providing the clock signal in the code transmission mode and the code receive mode.

20. An access control apparatus, comprising:

a key assembly, comprising;

means having a portion receiving at least one time division binary key code and a portion providing the received key codes via an output signal therefrom; and

a key code storage unit, having a code storage mode, a code receive mode and a code transmission mode, the key code storage unit having a portion for receiving the time division binary key codes from said means providing the key codes via the output signal therefrom in the code receive mode, the key code storage unit having a portion for storing at least one of the key codes received by the key code storage unit in the code storage mode, and the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode, the key code storage unit having a portion receiving a signal and clearing the key code stored in the key code storage unit in response to the received signal; and

a lock assembly having a portion for receiving the key code storage unit output signal having the key code stored in the key code storage unit encoded therein and a portion for providing an output signal for clearing the key code stored in the key code storage unit in response to the lock assembly receiving the key code storage unit output signal, the lock assembly output signal for clearing the key code from the key code storage unit being received by the key code storage unit and the key code stored in the key code storage unit being cleared from the key code storage unit in response to the received clock assembly output signal for clearing the key code.

21. The apparatus of claim 20 wherein the lock assembly is defined further to include:

a lock decoder and comparator assembly having a portion for receiving the key code from the key code storage unit and providing an output signal in response to receiving the key code for clearing the key code from the key code storage unit, the lock decoder and comparator output signal being received via the key code storage unit and the key code stored in the key code storage unit being cleared in response to the received lock decoder and comparator assembly output signal.

22. The apparatus of claim 21 defined further to include:

a data synchronization assembly generating an output clock signal; and

wherein the key code storage unit includes a portion receiving the clock signal for clocking the key code stored in the key code storage unit from the key code storage unit in the code transmission mode.

23. The apparatus of claim 22 wherein the lock decoder and comparator assembly includes a portion receiving the clock signal generated via the data synchronization assembly for clocking the key code into a portion of the lock decoder and comparator assembly, the lock decoder and comparator assembly having a predetermined lock code encoded therein and a portion comparing the received key code with the lock code and providing one output signal in response to an identical comparison of the key code and the lock code and providing the output signal for clearing the key code from the key code storage unit in response to a difference between the compared key code and lock code.

24. The apparatus of claim 23 wherein the lock assembly is defined further to include:

a lock control assembly, having a locked position, an unlocked position, and a portion receiving the lock decoder and comparator assembly outPut signal provided in response to an identical comparison of the key code and the lock code, the lock control assembly being positioned in the unlocked position in response to a received lock decoder and comparator assembly output signal indicating an identical comparison between the key code and the lock code.

25. The apparatus of claim 24 wherein the lock control assembly is defined further to include a portion providing an output signal in response to the positioning of the lock control assembly in the unlocked position;

and wherein the key code storage unit is defined further to include a portion receiving the lock control assembly output signal indicating the positioning of the lock control assembly in the unlocked position and clearing the key code from the key code storage unit in response thereto.

26. The apparatus of claim 25 wherein the lock control assembly is defined further to include:

a lock mechanism having a locked and an unlocked position;

a lock pin connected to the lock mechanism movable in a locking direction to a position positioning the lock mechanism in the locked position, and movable in an unlocking direction to a position positioning the lock mechanism in the unlocked position;

means connected to the lock pin biasing the lock pin in the unlocking direction;

means having a portion removably connected to the lock pin and another portion receiving the lock decoder and comparator output signal indicating an identical comparison between the lock code and the key code, said means preventing movement of the lock pin in the unlocking direction when connected to the lock pin, the lock pin being biased in the unlocking direction positioning the lock mechanism in the unlocked position upon the removal of the portion of said means removably connected to the lock pin in response to the lock decoder and comparator output signal indicating an identical comparison between the key code and the lock code; and

means having a portion engageable with a portion of the lock pin in one position of the lock pin, said means providing the output signal indicating the positioning of the lock control assembly in the unlocked position in the position of the lock pin positioning the lock mechanism in the unlocked position.

27. The apparatus of claim 23 wherein the lock decoder and comparator assembly is defined further to include:

a lock code generator having the lock code encoded therein and a portion receiving the clock signal generated via the data synchronization assembly, the lock code generator providing the lock code via an output signal in response to a received clock signal; and

means receiving the key code and the lock code generator output signal, comparing the key code and the lock code, and providing the lock decoder and comparator assembly output signal indicating a difference between the lock code and the key code.

28. A key assembly, comprising:

a data synchronization assembly generating an output clock signal;

a key receiver assembly having a portion receiving time division binary key codes and providing the received key codes via a key receiver assembly output signal;

a key code storage shift register having a portion receiving time division binary key codes via the key receiver assembly output signal and the data synchronization assembly clock signal, the received key codes being clocked into the key code storage shift register in a code receive mode, the key code storage shift register having a portion storing at least one of the received key codes in a code storage mode, and the key code storage shift register having a portion for receiving the data synchronization assembly clock signal and clocking the key code stored in the key code storage shift register from the key code storage shift register in a code transmission mode.

29. The apparatus of claim 28 wherein the key receiver assembly is defined further to include:

a receiver speaker receiving key codes via an acoustIcal data link; and

means receiving the key codes via a direct wire data link.

30. An access control assembly, comprising:

a key assembly, comprising;

a key receiver assembly receiving time division binary key codes and providing an output signal corresponding to the received key codes;

a key code storage unit, having a code storage mode, a code receive mode, and a code transmission mode, the key code storage unit having a portion for receiving the key codes via the key receiver assembly output signal in the code receive mode, the key code storage unit having a portion storing at least one of the key codes received by the key code storage unit in the code storage mode, and the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in the code transmission mode; and

a lock assembly, comprising;

a lock decoder and comparator assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion providing an output signal in response to the lock decoder and comparator assembly receiving a key code storage unit output signal having encoded therein a key code; and

a lock control assembly having a locked position and an unlocked position, the lock control assembly having a portion for receiving the lock decoder and comparator assembly output signal and positioning the lock control assembly in the unlocked position in response to a received lock decoder and comparator assembly output signal.

31. An access control assembly, comprising:

a data synchronization assembly generating and providing a clock signal;

a key assembly, comprising;

a key decoder assembly having a portion for receiving a predetermined time division binary lock recognition code, the key decoder assembly having a portion for providing an output signal in response to the key decoder assembly receiving a lock recognition code having a predetermined code format; and

a key code storage unit having a code transmission mode and a portion for storing a predetermined time division binary key code, the key code storage unit having a portion for receiving the key decoder assembly output signal and conditioning the key code storage unit in the code transmission mode in response to receiving the key decoder assembly output signal, the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in response to receiving the key decoder assembly output signal; and

a lock assembly, comprising;

a lock recognition code generator having a portion storing a predetermined time division binary lock recognition code, and a portion providing an output signal having the lock recognition code encoded therein, the lock recognition code provided via the lock recognition code generator output signal being received by the key decoder assembly; and

a lock decoder and comparator assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion providing an output signal in response to the lock decoder and comparator assembly receiving a key code storage unit output signal having encoded therein a key code having a predetermined code format.

32. An access control assembly, comprising:

a data synchronization assembly generating and providing a clock signal;

a key assembly, comprising;

a key decoder assembly having a portion for receiving a predetermined time division binary lock recognition code, the key decoder assembly having a portion for providing an output signal in response to the key decoder assembly receiving a lock recognition code having a predetermined code format; and

a key code storage unit having a code transmission mode and a portion for storing a predetermined time division binary key code, the key code storage unit having a portion for receiVing the key decoder assembly output signal and conditioning the key code storage unit in the code transmission mode in response to receiving the key decoder assembly output signal, the key code storage unit having a portion providing an output signal having the key code stored in the key code storage unit encoded therein in response to receiving the key decoder assembly output signal; and

a lock assembly, comprising;

a lock recognition code generator having a portion storing a predetermined time division binary lock recognition code, and a portion providing an output signal having the lock recognition code encoded therein, the lock recognition code provided via the lock recognition code generator output signal being received by the key decoder assembly; and

a lock decoder and comparator assembly having a portion storing a predetermined time division binary lock code, the lock decoder and comparator assembly having a portion for receiving the key code storage unit output signal having the key code encoded therein and a portion for comparing the received key code encoded in the key code storage unit output signal with the lock code stored in the lock decoder and comparator assembly and providing an output signal in response to an identical comparison of the lock code and the key code.

33. A method for operating lock assembly utilizing a key assembly adapted to receive time division binary key codes, the lock assembly having a time division binary lock code uniquely identifying the lock assembly, comprising the steps of:

conditioning the key assembly in a code receive mode for receiving time division binary key codes;

receiving the time division binary key codes via the key assembly;

conditioning the key assembly in a code storage mode for storing one of the receiving key codes;

storing one of the received key codes in the key assembly;

conditioning the key assembly in the code transmission mode for providing a signal having the key code stored in the key assembly encoded therein;

generating a signal having the key code stored in the key assembly encoded therein, the signal having the key code encoded therein being provided via the key assembly;

receiving the signal from the key assembly having the key code encoded therein via the lock assembly;

comparing the received key code with the lock code uniquely identifying the lock assembly;

generating a signal indicating a difference between the received key code and the lock code;

receiving via the key assembly the signal from the lock assembly indicating a difference between the key code and the lock code; and

clearing the key code stored in the key assembly from the key assembly in response to receiving the signal indicating a difference between the key code and the lock code.

34. A method for operating a lock mechanism having a locked position and an unlocked position wherein the lock mechanism is controlled via a lock assembly utilizing the key assembly adapted to receive time division binary key codes, the lock assembly having a time division binary lock code uniquely identifying the lock assembly, comprising the steps of:

conditioning the key assembly in a code receive mode for receiving the time division binary key codes;

receiving the time division binary key codes via the key assembly;

conditioning the key assembly in a code storage mode for storing one of the received key codes;

storing one of the received key codes in the key assembly;

conditioning the key assembly in a code transmission mode for providing a signal having the key code stored in the key assembly encoded therein;

generating a signal having the key code stored in the key assembly encoded therein, the signal having the key code encoded therein being provided via the key assembly;

receiving the signal from the key assembly having the key code encoded therein via the lock assembly;

comparing the received key code with the lock Code uniquely identifying the lock assembly;

generating a signal indicating an identical comparison between the received key code and the lock code;

unlocking the lock mechanism in response to the signal indicating an identical comparison between the lock code and the key code;

generating a signal indicating the unlocked status of the lock mechanism via the lock assembly;

receiving the signal indicating the unlocked status of the lock mechanism via the key assembly; and

clearing the key code stored in the key assembly from the key assembly in response to the received signal indicating the unlocked status of the lock mechanism.

35. A method for operating a lock mechanism having a locked position and an unlocked position wherein the lock mechanism is controlled by a lock assembly, having a time division binary lock code uniquely identifying the lock assembly, utilizing a key assembly adapted to receive time division binary key codes, comprising the steps of:

conditioning the key assembly in a code receive mode for receiving time division binary key codes;

receiving time division binary key codes via the key assembly;

conditioning the key assembly in a code storage mode for storing one of the received key codes;

storing one of the received key codes in the key assembly;

conditioning the key assembly in a code transmission mode for providing a signal having the key code stored in the key assembly encoded therein;

generating a signal having the key code stored in the key assembly encoded therein, the signal having the key code encoded therein being provided via the key assembly;

receiving the signal from the key assembly having the key code encoded therein via the lock assembly;

comparing the received key code with the lock code uniquely identifying the lock assembly;

generating a signal indicating an identical comparison between the received key code and the lock code;

generating a signal indicating a difference between the compared key code and lock code;

unlocking the lock mechanism in response to the signal indicating an identical comparison between the lock code and the received key code;

generating a signal indicating the unlocked status of the lock mechanism;

receiving via the key assembly the signal from the lock assembly indicating a difference between the lock code and the key code and receiving via the key assembly the signal from the lock assembly indicating the unlocked status of the lock mechanism; and

clearing the key code stored in the key assembly from the key assembly in response to the received signal indicating a difference between the lock code and the key code and clearing the key code stored in the key assembly from the key assembly in response to the received signal indicating the unlocked status of the lock mechanism.

36. A method for operating a lock mechanism having a locked position and an unlocked position wherein the lock mechanism is controlled by a lock assembly utilizing a key assembly having a time division binary key code encoded therein, the lock assembly having a time division binary lock code uniquely identifying the lock assembly and a time division binary lock recognition code having a predetermined code format, comprising the steps of:

generating a signal having the predetermined time division binary lock recognition code encoded therein via the lock assembly, the lock recognition code having a predetermined code format;

receiving the signal having the lock recognition code encoded therein via the key assembly;

generating a signal, having the time division binary key code encoded therein, via the key assembly in response to a received signal encoded with the lock recognition code having the predetermined code format;

receiving the signal from the key assembly encoded with the key code via the lock assembly;

comparing the received key code with the predetermined time division binary lock code;

generating a siGnal in response to an identical comparison between the received key code and the lock code; and

unlocking the lock mechanism in response to the signal indicating an identical comparison between the key code and the lock code.

37. The method of claim 36 defined further to include the steps of:

generating a signal indicating the unlocked status of the lock mechanism via the lock assembly;

receiving the signal indicating the unlocked status of the lock mechanism via the key assembly; and

clearing the key code from the key assembly in response to a received signal indicating the unlocked status of the lock mechanism.

38. The method of claim 37 defined further to include the steps of:

generating a signal in response to a difference between the compared key code and lock code via the lock assembly;

receiving the signal indicating a difference between the compared key code and lock code via the key assembly; and

clearing the key code from the key assembly in response to the received signal indicating a difference between the compared lock code and key code.