Device for decoding pulse-coded data

• US 3,913,100 A
• Filed: 12/20/1973
• Issued: 10/14/1975
• Est. Priority Date: 12/22/1972
• Status: Expired due to Term

• Current Assignee: Albert Janex
• Original Assignee: Albert Janex
• Inventors: Janex, Albert
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US05/426,528
• Time in Patent Office: 663 Days
• Field of Search: 343/5DP,6.8LC,6.5LC 329/107 328/119
• US Class Current: 342/42
• CPC Class Codes: G01S 13/784 Coders or decoders therefor; Degarbling systems; Defruiting systems
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A decoder device for decoding binary codes words each formed by a sequence of (n-1) logic conditions at a clock period theta . The code words are contained within a pair of '"'"''"'"''"'"''"'"'frame'"'"''"'"''"'"''"'"' pulses. A high clock frequency is used with a unique arrangement of timing circuits minimizes the number of shift register stages required in the decoding circuitry. The circuits allow for pulse time position tolerances of + OR - Delta theta and a corresponding unity recognition probability band between theta + Delta theta and theta - Delta theta .

Claims

1. A device for decoding pulse sequences of (n-1) logic conditions each 0 or 1 spaced by one clock period theta , thereby determining 2n 1 normal codes, in which said sequence is marked by an initial pulse F1o, and which is arranged to recognize a pulse delayed S theta + OR - Delta theta from said F1o pulse, where Delta theta is a time displacement tolerance, comprising the combination of:

a first timing circuit having a time constant 2 Delta theta responsive to said sequence to be triggered by each pulse thereof including, initially, said F1o pulse;

a shift register having at least n stages, the input of which is responsive to the 2 Delta theta width pulse output of said first timing circuit;

a clock for generating timing pulses having a period theta connected to advance said shift register one stage each theta period, said clock including a pulse generator operating at a frequency (k/ theta ) and a divider-by-k circuit responsive to said pulse generator, said divider having an enable input and said K being an integer much greater than (1/2 Delta );

a second timing circuit having a time constant Delta theta , responsive to the output of said first timing circuit;

a third timing circuit having a time constant T, responsive to the output of said second timing circuit, said third timing circuit being connected to said divider enable input to synchronize said clock for time T, from pulse F1o delayed by Delta theta , said T, being a time substantially longer than the longest of said sequence anticipated; and

a decoder coupled to n-1 adjacent shift register outputs in parallel, at time (n+1) theta after said F1o pulse, conditions 0 and 1 along said register outputs representing said word to be decoded.

2. A decoder device according to claim 1, for processing encoded words which comprise, in addition to the (n-1) logic conditions determining 2n 1 normal codes and the pulse F1o, and nth logic condition corresponding to a specific code X and an end pulse F2o, the time interval (n+1) theta from F1o to F2o being determined with tolerance + or - Delta theta , the said device including;

(n+2) stages in said shift register;

a first three-input coincidence circuit which, for a time T2 following the occurrence of F1o, is connected to produce a signal when simultaneously F1o and F2o enter the (n+2)th and 1st stages of said shift register whose outputs are connected to two inputs of the first coincidence circuit, T2, determined by timing circuit connected to the third input of the said first coincidence circuit, being slightly longer than (n+1) theta + 2 Delta theta ;

a first decoder connected from outputs of ranks 2, 3, . . . (x-1), (x+1), . . . , (n+1 of the shift register for decoding normal codes and a second decoder connected from output of rank x for decoding the specific code X as well as a first memory and a second memory wherein outputs of the first decoder and the second decoder are respectively stored under the control of a signal delivered from the first coincidence circuit, and in which said T, is defined as substantially longer than (N+1) theta + 2 Delta theta .

3. A decoder device according to the claim 2, for processing specific codes including, after a word made of n logic conditions within a frame determined by pulses F1o and F2o, from one to q words framed by pulse pairs F11 and F21, F12 and F22, . . . , F1q and F2q the numbers one to q determining specific codes, time intervals between those frame pulses being equal to (n+1) theta with a tolerance + or - Delta theta and time intervals between F2o and F11, F21 and F12, . . . , F2q 1 and F1q being equal to m theta with a tolerance of + or - Delta theta , the said device also comprising;

(n+2+m) stages in said shift register, a second four-input coincidence circuit connected so that, after a time T3 from the occurrence of F1o, it operates to deliver a signal when pulses F2o, F11 and F21 simultaneously enter the (n+2+m)th, (n+2)th and 1st stages of said shift register whose outputs are connected to the three inputs of a second coincidence circuit, then when pulses including F21, F12 and F22, and on up to F2q 1, F1q, and F2q, T3, as determined by a timing circuit connected to the fourth input of the said second coincidence circuit, said last mentioned timing circuit delivering a signal longer than (n+1+m) theta + 2 Delta theta , and said T, being defined as substantially longer than ((n+1)(q+1)+mq) theta + (2q+1) Delta theta ;

a counter, having a capacity (q+1), connected to be reset by the occurrence of each pulse F1o, which counts the number of signals from one to q delivered from the second coincidence circuit; and

means for synchronizing said clock, at rate theta , on each of the pulses F2o, F11, F21, F12, . . . , F2q 1, F1q.

4. A decoder device according to claim 3, wherein the means for synchronizing the clock, at rate theta , are characterized by the fact that they comprise:

a reoperable timing circuit, having a time constant theta , which is triggered under the control of the timing circuit having the time constant 2 Delta theta ;

a set of logic gates connected from said first coincidence circuit output and the outputs of the 1st and (n+2+m)the stages of said shift reigster so as to produce a signal when pulses F2o, F11, F21, . . . , or F1q enter the shift register, the said signal being applied to one of the two inputs of a third coincidence circuit whose other input is connected from output of the reoperable timing circuit having a time constant theta ;

a second timing circuit, having a time constant Delta theta , which is triggered when the third coincidence circuit is on and having an output connected to said divider-by-k enable input so as to prevent said divider-by-k from operating from a duration Delta theta following the time theta defined by the beginning of one of the pulses F2o, F11, . . . F1q, entering the shift register.

5. A decoder device according to claim 4, characterized by the fact that:

the timing circuit, having a time constant theta , is constituted by a reoperable monostable circuit having a free-running duration theta ;

at least one of the other timing circuits, having a time constant to, is constituted by monostable circuits having time constant to, said circuits switched as soon as a pulse leading edge is applied to their input and are reset after a time period to.

6. A decoder device according to claim 4, for processing secondary radar transponder replies comprising normal codes, including code X, made of n conditions 0 or 1 bracketed by pulses F1o and F2o, position identification specific codes formed from a normal code followed by its repetition q 1 spaced by a standard time interval m theta , and of specific mayday codes formed from a normal code followed by q codes of n conditions bracketed by pulse pairs F11 and F21, F12 and F22, F13 and F23, said pulse pairs being time spaced by a standard time interval of m theta , the said decoder device comprising:

means connecting the outputs of the counter of capacity (q+1

     4), where numbers q 1 and q 3 are indicated, connecting to two independent integrator circuits, which independently decode position identification specific code and mayday specific code, the time constant of the said integrator circuiT being long enough so that they are not sensitive to numerous successive markings of duration close to the reply repetition period tr.

7. A decoder device according to the claim 6, capable of processing specific position identification codes, called '"'"''"'"''"'"''"'"'SPI codes'"'"''"'"''"'"''"'"' constituted by a normal code followed, at a standard interval m theta , by a pulse called an SPI pulse, comprising:

a flip-flop whose enable input is connected from the set of logic gates having its erasing input connected from the output of the second coincidence circuit so as to turn its condition when said SPI pulse enters the shift register, and means responsive to said second coincidence circuit to deliver a signal before the end of time T1, thereby to reset said flip-flop;

an integrator, connected from the said flip-flop output, to decode said SPI codes, the said integrator time constant being so long that it is not sensitive to short duration condition changes of flip-flop output, but short enough to be sensitive to numerous successive changes of duration close to the reply repetition period tr.

8. A decoder device according to claim 3, including means which allow the encoded word to be processed only if its pulse F1o is applied to the overall device input between times Tau 1 and Tau 2 following reference signal transmission, the said means comprising:

a timing circuit having a time constant Tau 1, which is triggered by the reference signal, and a time circuit having a time constant ( Tau 2 - Tau

     1), which is triggered at the end of time Tau 1, said circuits being cascade connected; and

means connecting the output of said timing circuit having time constant ( Tau 2 - Tau

     1) to a specific enable input triggering said first timing circuit having timing constant Delta theta .

9. A decoder device according to claim 8, wherein said first timing circuit has a time constant Delta theta and is provided with a specific triggering enable input comprising:

a flip-flop provided with a data input connected from the output of said timing circuit having a time constant ( Tau 2 - Tau

     1) and a pulse input connected from the output of said timing circuit having time constant 2 Delta theta ; and

a delay circuit, having a delay constant Delta theta , comprising a serially connected resistor and capacitor, said capacitor having one of its electrodes connected to ground and the other connected to the input of the timing circuit having said time constant T1.