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Planar circuit fabrication process

  • US 3,913,219 A
  • Filed: 05/24/1974
  • Issued: 10/21/1975
  • Est. Priority Date: 05/24/1974
  • Status: Expired due to Term
First Claim
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1. A method for fabricating a plurality of individual planar resonant tags each having at least one self-contained operative tuned circuit with integrally formed circuit elements including at least one inductor and at least one capacitor, said method comprising the steps of:

  • providing an insulative substrate web of material of predetermined thickness and dielectric characteristics and with a conductive surface on each opposite side thereof;

    printing with an etchant-resistive material a first repetitive circuit pattern including the formation of at least one inductor and a conductive area serving as a portion of said at least one capacitor on one conductive surface of said substrate web;

    printing with an etchant-resistive material a second repetitive circuit pattern on the other conductive surface of said substrate web in predetermined relation to said first repetitive circuit pattern and including the formation of a conductive area in alignment with the conductive area on said one conductive surface and serving as a portion of said at least one capacitor;

    said first and second printed circuit patterns providing said planar tags with said conductive areas and the interposed dielectric material provided by said substrate web defining said at least one capacitor;

    etching said first and second circuit patterns to remove unprinted portions of said conductive surfaces on both sides of said substrate web thereby to provide repetitive first and second cooperative conductive circuit patterns conforming to said printed circuit patterns; and

    separating cooperative circuit patterns to provide individual planar resonant tags.

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