Planar circuit fabrication process
First Claim
Patent Images
1. A method for fabricating a plurality of individual planar resonant tags each having at least one self-contained operative tuned circuit with integrally formed circuit elements including at least one inductor and at least one capacitor, said method comprising the steps of:
- providing an insulative substrate web of material of predetermined thickness and dielectric characteristics and with a conductive surface on each opposite side thereof;
printing with an etchant-resistive material a first repetitive circuit pattern including the formation of at least one inductor and a conductive area serving as a portion of said at least one capacitor on one conductive surface of said substrate web;
printing with an etchant-resistive material a second repetitive circuit pattern on the other conductive surface of said substrate web in predetermined relation to said first repetitive circuit pattern and including the formation of a conductive area in alignment with the conductive area on said one conductive surface and serving as a portion of said at least one capacitor;
said first and second printed circuit patterns providing said planar tags with said conductive areas and the interposed dielectric material provided by said substrate web defining said at least one capacitor;
etching said first and second circuit patterns to remove unprinted portions of said conductive surfaces on both sides of said substrate web thereby to provide repetitive first and second cooperative conductive circuit patterns conforming to said printed circuit patterns; and
separating cooperative circuit patterns to provide individual planar resonant tags.
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Accused Products
Abstract
A process for the high volume fabrication of planar electrical circuits having precision electrical characteristics and especially adapted for use in electronic security systems employing resonant circuits. A multiplicity of circuits are formed by high speed printing techniques on opposite surfaces of an insulative web and the individual circuits separated for use.
147 Citations
30 Claims
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1. A method for fabricating a plurality of individual planar resonant tags each having at least one self-contained operative tuned circuit with integrally formed circuit elements including at least one inductor and at least one capacitor, said method comprising the steps of:
- providing an insulative substrate web of material of predetermined thickness and dielectric characteristics and with a conductive surface on each opposite side thereof;
printing with an etchant-resistive material a first repetitive circuit pattern including the formation of at least one inductor and a conductive area serving as a portion of said at least one capacitor on one conductive surface of said substrate web;
printing with an etchant-resistive material a second repetitive circuit pattern on the other conductive surface of said substrate web in predetermined relation to said first repetitive circuit pattern and including the formation of a conductive area in alignment with the conductive area on said one conductive surface and serving as a portion of said at least one capacitor;
said first and second printed circuit patterns providing said planar tags with said conductive areas and the interposed dielectric material provided by said substrate web defining said at least one capacitor;
etching said first and second circuit patterns to remove unprinted portions of said conductive surfaces on both sides of said substrate web thereby to provide repetitive first and second cooperative conductive circuit patterns conforming to said printed circuit patterns; and
separating cooperative circuit patterns to provide individual planar resonant tags.
- providing an insulative substrate web of material of predetermined thickness and dielectric characteristics and with a conductive surface on each opposite side thereof;
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2. The method according to claim 1 wherein said conductive surface providing step includes the steps of:
- providing an electrically insulative web of material of predetermined thickness and having a low dissipation factor at a frequency of interest and a stable dielectric constant;
treating the opposite surfaces of said web by corona discharge to enhance the bonding characteristics of said surfaces; and
laminating first and second conductive foils respectively to said treated surfaces.
- providing an electrically insulative web of material of predetermined thickness and having a low dissipation factor at a frequency of interest and a stable dielectric constant;
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3. The method according to claim 1 wherein said separating step includes:
- laminating said web containing said cooperative circuit patterns to at least a first sheet;
die cutting each of said cooperative circuit patterns representing an individual planar resonant tag from waste material; and
separating said waste material from said first sheet containing individual planar resonant tags.
- laminating said web containing said cooperative circuit patterns to at least a first sheet;
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4. The method according to claim 1 wherein said separating step includes:
- laminating said web containing said cooperative circuit patterns to at least a first sheet;
die cutting each of said cooperative circuit patterns representing an individual planar resonant tag; and
removing from said first sheet said individual planar resonant tags.
- laminating said web containing said cooperative circuit patterns to at least a first sheet;
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5. The method according to claim 1 wherein said conductive surface providing step inclUdes the steps of:
- providing an electrical insulative web of material of predetermined thickness and having a low dissipation factor at a frequency of interest and a stable dielectric constant;
treating the opposite surfaces of said web to enhance the bonding characteristic of said surfaces; and
laminating first and second conductive foils respectively to said treated surfaces.
- providing an electrical insulative web of material of predetermined thickness and having a low dissipation factor at a frequency of interest and a stable dielectric constant;
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6. The method according to claim 1 wherein said printing steps include the printing of registration marks together with said circuit patterns on the respective conductive surfaces of said substrate web, said registration marks being in physical interconnection between adjacent ones of at least one of said repetitive circuit patterns.
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7. The method according to claim 1 wherein said printing steps are accomplished before provision of said conductive surfaces on said substrate web.
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8. The method according to claim 1 wherein said printing steps are accomplished after provision of said conductive surfaces of said substrate web.
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9. The method according to claim 1 wherein said etching step is accomplished without removal of said etchant-resistive material defining said circuit patterns.
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10. The method according to claim 1 wherein said printing steps include printing with an etchant-resistive material said repetitive circuit patterns on said conductive surfaces without prior cleaning of said conductive surfaces.
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11. The method according to claim 1 wherein said printing steps include printing with a non-photoresponsive etchant-resistive material.
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12. The method according to claim 1 wherein at least one of said printing steps includes printing with said etchant-resistive material a plurality of fusible links each in circuit with an associated one of said repetitive circuit patterns.
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13. The method according to claim 1 wherein said printing steps include high speed web fed press printing.
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14. The method according to claim 1 further including the step of electrically connecting said first and second cooperative conductive circuit patterns of each of said planar circuits through said substrate at at least one selected position thereof.
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15. The method according to claim 2 wherein said electrical connection is formed by welding said first and second cooperative conductive circuit patterns through said substrate at said at least one selected position thereof.
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16. The method according to claim 15 wherein said welding step includes:
- disposing each of said circuit patterns at a heated base to soften said substrate; and
applying an ultrasonic welding tip to said circuit pattern at said selected position to form said electrical connection.
- disposing each of said circuit patterns at a heated base to soften said substrate; and
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17. The method according to claim 15 wherein said welding step includes the provision of a cold weld between said first and second conductive circuit patterns at said at least one selected position to form said electrical connection.
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18. The method according to claim 15 wherein said welding step includes the provision of an ultrasonic weld between said first and second conductive circuit patterns at said at least one selected position to form said electrical connection.
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19. The method according to claim 18 wherein said ultrasonic weld is provided by a multiple sector welding tip operative to provide multiple spot welds between said first and second conductive circuit patterns.
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20. The method according to claim 1 wherein said printing steps include the printing of registration marks together with said circuit pattens on the conductive surfaces of said substrate web.
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21. The method according to claim 20 including the further step of punching one or more holes through said substrate web at selected positions with respect to said first and second circuit patterns to serve as registration elements.
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22. The method according to claim 1 wherein said printing steps include the rotogravure printing of said circuit patterns.
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23. The method according to claim 11 wherein said printing steps furTher include printing with a black nitrocellulose ink to form said circuit patterns.
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24. The method according to claim 1 wherein said separating step includes:
- laminating said web containing said cooperative pairs of circuit pattern between first and second sheets;
die cutting each circuit pattern pair; and
separating said second sheet containing individual die cut planar circuits from said first sheet to provide individual planar resonant tags.
- laminating said web containing said cooperative pairs of circuit pattern between first and second sheets;
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25. The method according to claim 24 further including the step of slitting said second sheet along the length thereof to provide respective rolls of single planar circuits.
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26. The method according to claim 1 wherein said substrate web is polyethylene and wherein said conductive surfaces are aluminum foil.
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27. The method according to claim 26 wherein said aluminum foil is bonded to said polyethylene web with the dull side of said aluminum foil in contact with said web.
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28. The method according to claim 27 wherein one of said aluminum foils is of a thickness greater than the other to provide predetermined lower electrical resistance for planar inductors formed thereof as part of said planar circuit.
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29. The method according to claim 28 wherein said etching step includes etching the ones of said circuit patterns having aluminum foil of greater thickness at a higher rate than said other circuit pattern to provide the same etching time for said foils of different thicknesses.
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30. The method according to claim 27 wherein said printing steps include printing with an etchant-resistive material said repetitive circuit patterns on the shiny surfaces of said aluminum foil without prior cleaning of said shiny surfaces.
Specification