Data compression method and apparatus
First Claim
1. Apparatus for encoding successive identical groups of bits of binary data comprising:
- clocking means for forming a plurality of bit cells of uniform time durations and for defining the leading edge and midpoint of each bit cell, and bit pair encoder means responsive to the first of said successive groups of binary data and to said clocking means and comprising parallel in serial out shift register means for storing said groups of bits and gate means for detecting the binary character of adjacent uncoded bits shifted through said register means, said gate means responding to those bits of one binary characterization in said first group of bits by producing first control pulses at the midpoint of only those of the corresponding bit cells which immediately follow a bit cell in which no pulse occurs and which are immediately followed by a bit cell containing a bit of said one binary characterization, said gate means further responding to those of said bits of the other binary characterization in said first group of bits by producing second control pulses at the leading edge of only those of the corresponding bit cells which immediately follow a bit cell in which no pulse occurs and which are immediately followed by a bit cell containing a bit of said other binary characterization, detector means for detecting the number of said successive groups of bits, signal generating means responsive to the number of said successive groups, and to the state of the last bit of said first group of bits by producing third control pulses, said third control pulses consisting of five pulses, the first pulse occurring at the trailing edge of the bit cell corresponding to the last bit of said first group of bits, the second pulse occurring at least two bit cells displaced from said first pulse and occurring at the midpoint or leading edge of a bit cell depending upon whether the state of the last bit of said first group of bits is said one or said other binary characterization respectively, the third pulse displaced from said second pulse by 1 1/2 bit cells, the fourth pulse displaced from said third pulse by 1 1/2 bit cells, and the fifth pulse displaced from said fourth pulse by an amount which exceeds 1 1/2 bit cells by a multiple of 1/2 bit cells for each group of bits following said first group of bits, output state controller means for providing a bistable output signal containing transitions between separately identifiable states in response to either of said first, second or third control pulses.
0 Assignments
0 Petitions
Accused Products
Abstract
Data compression apparatus is disclosed which is operable in either a bit pair coding mode or a word coding mode depending on the degree of redundancy of the data to be encoded. Consecutive words of data to be encoded are compared and if the words are not identical within a predefined tolerance the data is encoded on a bit pair basis. The bit pair encoding produces transitions in the coded output signals at the beginning of the first of two bit cells which contain a discrete pair of 1'"'"''"'"'s and at the middle of the first of two bit cells which contain a discrete pair of 0'"'"''"'"'s. If the data to be encoded contains a sufficient number of consecutive identical words to permit a greater data compression on a word basis rather than a bit pair basis the first word in the consecutive identical words is encoded on a bit pair basis to identify the bit pattern and a unique transitional pattern incapable of being generated during bit pair coding is generated to identify the number of succeeding words which are identical with the first word.
41 Citations
8 Claims
-
1. Apparatus for encoding successive identical groups of bits of binary data comprising:
- clocking means for forming a plurality of bit cells of uniform time durations and for defining the leading edge and midpoint of each bit cell, and bit pair encoder means responsive to the first of said successive groups of binary data and to said clocking means and comprising parallel in serial out shift register means for storing said groups of bits and gate means for detecting the binary character of adjacent uncoded bits shifted through said register means, said gate means responding to those bits of one binary characterization in said first group of bits by producing first control pulses at the midpoint of only those of the corresponding bit cells which immediately follow a bit cell in which no pulse occurs and which are immediately followed by a bit cell containing a bit of said one binary characterization, said gate means further responding to those of said bits of the other binary characterization in said first group of bits by producing second control pulses at the leading edge of only those of the corresponding bit cells which immediately follow a bit cell in which no pulse occurs and which are immediately followed by a bit cell containing a bit of said other binary characterization, detector means for detecting the number of said successive groups of bits, signal generating means responsive to the number of said successive groups, and to the state of the last bit of said first group of bits by producing third control pulses, said third control pulses consisting of five pulses, the first pulse occurring at the trailing edge of the bit cell corresponding to the last bit of said first group of bits, the second pulse occurring at least two bit cells displaced from said first pulse and occurring at the midpoint or leading edge of a bit cell depending upon whether the state of the last bit of said first group of bits is said one or said other binary characterization respectively, the third pulse displaced from said second pulse by 1 1/2 bit cells, the fourth pulse displaced from said third pulse by 1 1/2 bit cells, and the fifth pulse displaced from said fourth pulse by an amount which exceeds 1 1/2 bit cells by a multiple of 1/2 bit cells for each group of bits following said first group of bits, output state controller means for providing a bistable output signal containing transitions between separately identifiable states in response to either of said first, second or third control pulses.
-
2. producing a transition between the separately identifiable states at the midpoint of the first of two successive bit cells to represent that the bit cells contain the complement of said first two bit data configuration;
-
3. Apparatus for reduced redundancy encoding of data comprising:
- a source of binary data, clock generator means for forming a plurality of bit cells of uniform time durations, and for defining the leading edge and midpoint of a bit cell, complementary bit pair encoder means responsive to said data and to said clock generator means, said encoder means including first gate means for producing first control pulses occurring at the leading edge of only those bit cells containing a bit of one binary characterization and which immediately follow a bit cell in which no pulse occurs and which are immediately followed by a bit cell containing a bit of said one binary characterization, said encoder means further including second gate mEans producing second control pulses at the midpoint of only those bit cells containing a bit of the other binary characterization and which immediately follow a bit cell in which no pulse occurs and which are immediately followed by a bit cell containing a bit of said other binary characterization, word comparator means responsive to said data and to said clock generator means for detecting consecutive identical words of data of predetermined bit length, control logic means responsive to said clock generator means and to detection of a predetermined number of consecutive identical words by said word comparator means for inhibiting said complementary bit pair detection means following detection of the complementary bit pairs in the first of the consecutive identical words, pulse generating means responsive to said clock generator means and to said control logic means and said word comparator means for producing third control pulses, said third control pulses consisting of five pulses, the first pulse occurring at the trailing edge of the bit cell corresponding to the last bit in the first of said consecutive identical words, the second pulse occurring at least 2 bit times delayed from said first pulse and at the leading edge or midpoint of a bit cell depending upon whether the state of the last bit of the first of said consecutive identical words is of said one or other binary characterization respectively, the third pulse occurring 1 1/2 bit cells delayed from said second pulse, the fourth pulse occurring 1 1/2 bit cells delayed from said third pulse, and the fifth pulse being delayed from said fourth pulse by an amount which exceeds 1 1/2 bit cells by 1/2 bit cell for each of the consecutive identical words following the first of said consecutive identical words, said control logic enabling said complementary bit pair detection means at the beginning of a bit cell and at least two bit cells delayed from the said fifth pulse, and output state controller means for providing a bistable output signal containing transitions between separately identifiable states in response to either of said first, second or third control pulses.
-
4. repeating steps 1 and 2 after a 2 or 2 1/2 bit cell time delay depending upon whether said fifth transition occurs at the beginning or midpoint of a bit cell respectively.
-
5. A method of communicating binary information on a communication medium, the medium exhibiting two separately identifiable states and being divided into a plurality of uniform bit cells comprising the steps of:
-
6. A method of communicating binary information on a communication medium, the medium exhibiting two separately identifiable states and being divided into a plurality of uniform bit cells comprising the steps of:
-
7. Apparatus for reduced redundancy encoding of consecutive identical groups of binary data comprising:
- clocking means for forming a plurality of bit cells of uniform time durations and for defining the edge and midpoint of each bit cell, means for detecting the number of consecutive identical groups of said data, means for identifying the binary character of the last bit of the first of the consecutive identical groups of bits, signal generating means responsive to said clocking means and to said detecting means and to said identifying means for generating a bilevel output signal containing a first transition at the trailing edge of the bit cell containing the last bit of said first group of bits, a second transition at least two bit cells displaced from said first transition and occurring at the midpoint or leading edge of a bit cell depending upon whether the state of the last bit of said first group of bits is of one binary character or the other binary character respectively, additional transitions separated by 1 1/2 bit cells and corresponding in number to the number of said groups of bits following said first group of bits.
-
8. Apparatus for reduced redundancy encoding of consecutive identical groups of binary data comprising:
- clocking means for forming a plurality of bit cells of uniform time duration and for defining the edge and midpoint of each bit cell, means for detecting the number of said consecutive groups of said data, means for identifying the binary character of the last bit of the first of the consecutive groups of bits, signal generating means responsive to said clocking means and to said detector means and to said identifying means for generating a bilevel output signal comprising a first transition occurring at the trailing edge of the bit cell containing the last bit of the first of the consecutive identical groups of bits, a second transition occurring at least two bit times delayed from said first transition and at the leading edge or midpoint of a bit cell depending upon whether the state of the last bit of the first of the consecutive identical groups of bits is of one binary character or the other binary character respectively, a third transition occurring 1 1/2 bit cells delayed from said second transition, a fourth transition occurring 1 1/2 bit cells delayed from said third transition, a fifth transition delayed from said fourth transition by an amount which exceeds 1 1/2 bit cells by 1/2 bit cell for each of the consecutive identical groups of bits following the first of the consecutive identical groups of bits.
Specification