D.C. motor control having gating control of a full-wave reactifier system

• US 3,914,674 A
• Filed: 05/10/1974
• Issued: 10/21/1975
• Est. Priority Date: 05/10/1974
• Status: Expired due to Term

• Current Assignee: Armor Elevator Co., Inc. (Kone Corporation)
• Original Assignee: Armor Elevator Co., Inc. (Kone Corporation)
• Inventors: Maynard, John T.
• Primary Examiner(s): Schaefer, Robert K.
• Assistant Examiner(s): Duncanson, Jr., W. E.
• Application Number:
  US05/468,860
• Time in Patent Office: 529 Days
• Field of Search: 187/29 318/331,341,345
• US Class Current: 388/819
• CPC Class Codes: H02P 3/14 by regenerative braking
• CPC Class Codes: H02P 7/2985 whereby the speed is regulated by measuring the motor speed and comparing it with a given physical value
• CPC Class Codes: Y10S 388/902 Compensation
• CPC Class Codes: Y10S 388/917 Thyristor or scr

Abstract

A D.C. motor is selectively connected to receive energizing power from a polyphase power source through a dual bridge rectifying system providing full-wave rectification and selectively operable to supply current of either polarity for motoring in either direction and regenerative operation. An improved gating control system includes a plurality of gating channels each operative for supplying gating pulses to one of the rectifying elements. Each channel includes three cascaded solidstate switching circuits operating in response to an analog output of a summing circuit receiving a compensated error signal, an alternating phase reference signal, and a constant reference signal for properly controlling the firing angle of the associated controlled rectifier. An input switching transistor circuit is connected to receive the analog output of the summing circuit and an output switching Darlington pair circuit selectively operates to operatively connect a storage capacitor to a primary winding of an output transformer having a secondary windng directly connected to the gating and cathode circuits of the controlled rectifier through insulated output leads. An intermediate switching Darlington pair circuit is connected between the input and output switching circuits and provides an output circuit in one channel connected to an input circuit of an output switching circuit in another channel so that the two inter-related channels will both render the associated rectifying devices conductive to energize the D.C. motor. Disable signals relating to the error signal polarity and the relative phase polarity are supplied to the input circuit of the intermediate switching circuit to disable the associated controlled rectifier.

Claims

1. A motor control circuit for energizing a D.C. motor from a polyphase power supply to maintain a regulated motor output by a gating system for a plurality of individual rectifier means connected to said power supply in a full-wave rectifying system wherein each of said rectifier means is selectively fired during a given half cycle of alternating current input and commutates during the successive half cycle of the alternating current input;

the improvement in pulse generating means for gating of the individual rectifier means comprising a plurality of gating control channels each operative for supplying a gating pulse to one of said rectifier means with each of said channels including first switching means having first input means operatively receiving a selectively variable firing control signal from command means and first output means selectively operable from a first condition to a second condition in response to said firing control signal and connected to second input means of second switching means having second output means selectively operable from a first condition to a second condition in response to said second condition of said first switching means, said second output means providing said second condition to operatively supply an output pulse to said associated rectifier means, said first output of said first switching means of each channel connected to second input means of second switching means of one other channel for operating said other channel and supplying an output pulse to the associated rectifier means of said other channel.

2. The circuit of claim 1, wherein each of said second output means includes energy storage means operatively connected to a primary winding of an output transformer having an output winding connected to selectively supply said output pulse to said associated rectifier means.

3. The circuit of claim 2, wherein each of said rectifier means includes a gating circuit and a cathode circuit, and said second output means includes a pair of conducting leads connected to said output winding and directly connected to said gating and cathode circuits.

4. The circuit of claim 1, wherein said motor control circuit includes signal-forming means establishing an error signal related to an output of said motor and a desIred output and selectively providing an enable signal and a disable signal to said first input means of each of said channels in response to the polarity of said error signal and selectively enabling and disabling said channels in response to said sensed error signal polarity.

5. The circuit of claim 1, wherein said motor control circuit includes disable means connected to said source and selectively supplying a disable signal to said first input means to selectively disable each channel in response to the relative phase relationship of said polyphase supply.

6. The circuit of claim 5, wherein said disable means includes a lag filter network.

7. The circuit of claim 1, wherein each of said channels includes third switching means having third input means receiving said selectively variable firing control signal and third output means connected to said first input means and operable from a first condition to a second condition in response to said control signal and conditioning said channel to supply an output pulse.

8. The circuit of claim 7, wherein said third input means for each channel includes summing means receiving said firing control signal and reference means connected to said polyphase supply and supplying an alternating reference signal to said summing means in response to the relative phase relationship of said polyphase supply, said third switching means selectively operating from said first condition to said second condition in response to the relative relationship between said firing control signal and said alternating reference signal.

9. The circuit of claim 8, wherein said reference means operatively supplies a constant reference signal to said summing means, said third switching means selectively operating from said first condition to said second condition in response to the relative relationship between said firing control signal and said alternating and constant reference signals.

10. The circuit of claim 7, wherein said reference means includes a lead filtering network coupled to said power supply and connected to said summing means through a lag filtering network.

11. The circuit of claim 7, wherein said third input means for each channel includes summing means receiving said firing control signal and reference means supplying a constant reference signal to said summing means, said third switching means selectively operating from said first condition to said second condition in response to the relative relationship between said firing control signal and said constant reference signal.

12. A motor control circuit for energizing a D.C. motor from a polyphase power supply to maintain a regulated motor output by a gating system for a plurality of individual rectifier means connected to said power supply in a full-wave rectifying system wherein each of said rectifier means is selectively fired during a given half cycle of the alternating current input and commutates during the successive half cycle of the alternating current input;

the improvement in a pulse generating means for gating of the individual rectifier means comprising a plurality of gating control channels each operative for supplying a gating pulse to one of said rectifying means having a cathode circuit and a gating circuit, each of said channels including a first switching circuit having a first input circuit operatively receiving a selectively variable firing control signal and a first output circuit selectively operable from a first condition to a second condition in response to said firing control signal and connected to a second input circuit of a second switching circuit having a second output circuit connected to a primary winding of an output transformer having an output winding directly connected to said gating and cathode circuits by first and second insulated leads and an energy storage capacitor operatively coupled to said primary winding, said second switching circuit operating from a first condition to a second condition and conducting energy from said storage Capacitor through said primary winding and supplying said gating pulse to said gating circuit in response to the condition transfer of said first switching circuit, said first output circuit of said first switching circuit of each channel connected to a second input of a second switching circuit of another channel to operatively supply a gating pulse to a gating circuit of another rectifier means in response to said condition transfer of said first switching circuit.

13. The circuit of claim 12, wherein said first switching circuit includes a switching transistor having a base circuit operatively responding to said firing control signal and a collector circuit connected to said second input circuit and to a voltage dividing circuit including a first impedance connected to an unregulated voltage source and a second impedance connected to a reference potential.

14. The circuit of claim 13, wherein said second switching circuit includes a Darlington pair transistor circuit operating as a NOR circuit and having a base circuit connected to said voltage dividing circuit.

15. The circuit of claim 12, wherein said control circuit includes signal-forming means establishing an error signal related to an actual motor output and a desired output and selectively supplying an enable signal and a disable signal to said first input circuit of each channel in response to the sensed relative error signal polarity of each channel including disable means connected to said polyphase supply and to said first input circuit through a lag filter network and supplying a disable signal in response to the relative polarity of a phase of said supply and a third switching circuit having a third input circuit including a summing circuit operatively connected to respond to said error signal by receiving said firing control signal and receiving an alternating reference signal from said power supply through a lead and lag filtering network and a constant reference signal from a constant potential source.