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Time jitter generator

  • US 3,916,329 A
  • Filed: 05/01/1974
  • Issued: 10/28/1975
  • Est. Priority Date: 05/01/1974
  • Status: Expired due to Term
First Claim
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1. A circuit for introducing controlled delay into a train of data pulses, comprising:

  • a series of N one-shot circuits connected in cascade, each arranged to provide an output pulse with a leading edge initiated in response to the trailing edge of the output pulse from the preceding stage in said series, each one-shot circuit being of the type wherein the width of said output pulse is variable with the level of a control voltage applied to the one-shot circuit;

    at least one data shift register comprising N flip-flops connected in cascade, each flip-flop being clocked by the trailing edge of an output pulse from a corresponding one-shot circuit in said series to assume a binary state determined by the state of the preceding flip-flop in said data shiftregister;

    means for applying a common control voltage to all of said oneshot circuits;

    means for applying a binary data pulse train to the first flipflop in said data shift register; and

    means for applying a clock pulse train to the first one shot in said series, transitions in said data pulse train being synchronized to transitions in said clock pulse train.

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