Time jitter generator

• US 3,916,329 A
• Filed: 05/01/1974
• Issued: 10/28/1975
• Est. Priority Date: 05/01/1974
• Status: Expired due to Term

• Current Assignee: Norris C. Hekimian, Robert M. Ginnings
• Original Assignee: Norris C. Hekimian, Robert M. Ginnings
• Inventors: Hekimian, Norris C., Ginnings, Robert M.
• Primary Examiner(s): Schaefer, Robert K.
• Assistant Examiner(s): Feldhaus, John J.
• Application Number:
  US05/465,803
• Time in Patent Office: 545 Days
• Field of Search: 307/208,269 328/55,155,37 329/104
• US Class Current: 327/265
• CPC Class Codes: H04L 1/205 jitter monitoring

Abstract

A time jitter generator, for use in testing the impact of jitter on digital equipment, introduces a continuously variable static delay and/or time jitter on digital data and clock pulse trains. Static delay is achieved by passing the clock train through a series of cascaded one shot circuits, each one-shot triggering on the trailing edge of the pulse from the preceding circuit. The trailing edge of each one-shot pulse also clocks data into a corresponding stage of a shift register so that each shift register stage is clocked at a different time depending upon the pulse widths of the one-shot circuits. These widths are adjustable under operator control to permit controlled static delay to be achieved over a relatively large continuous range of delay. The control voltage employed to control one-shot pulse width is applied through a delay-responsive feedback loop to eliminate temperature effects. Jitter modulation is achieved by summing a time-varying jitter signal with the control voltage, the jitter signal having a frequency lying outside the bandwidth of the static delay loop.

Claims

1. A circuit for introducing controlled delay into a train of data pulses, comprising:

a series of N one-shot circuits connected in cascade, each arranged to provide an output pulse with a leading edge initiated in response to the trailing edge of the output pulse from the preceding stage in said series, each one-shot circuit being of the type wherein the width of said output pulse is variable with the level of a control voltage applied to the one-shot circuit;

at least one data shift register comprising N flip-flops connected in cascade, each flip-flop being clocked by the trailing edge of an output pulse from a corresponding one-shot circuit in said series to assume a binary state determined by the state of the preceding flip-flop in said data shiftregister;

means for applying a common control voltage to all of said oneshot circuits;

means for applying a binary data pulse train to the first flipflop in said data shift register; and

means for applying a clock pulse train to the first one shot in said series, transitions in said data pulse train being synchronized to transitions in said clock pulse train.

2. The circuit according to claim 1 further comprising:

means for providing a jitter signal having a time-varying amplitude; and

means for summing said jitter signal with said common control voltage applied to said one-shot circuits.

3. The circuit according to claim 1 further comprising:

a frequency divider arranged to receive said clock pulse train and provide a frequency-divided pulse train having a repetition rate which is less than the repetition rate of said clock pulse train;

a measurement shift register comprising N flip-flops connected in cascade, each flip-flop being clocked by the trailing edge of an output pulse from a corresponding one-shot circuit in said series to assume a binary state determined by the binary state of the preceding flip-flop in said measurement shift register;

means for applying said frequency-divided pulse train to the first flip-flop in said measurement shift register;

phase detection means for providing a further signal having an amplitude which is a predetermined function of the phase difference between said frequency-divided pulse train and output pulses derived from the Nth flip-flop of said measurement shift register; and

control means responsive to said further signal for providing said common control voltage.

4. The circuit according to claim 3 wherein said further signal is a DC signal having an amplitude proportional to said phase difference, and wherein said control means comprises:

an integrator connected to receive and integrate said further signal; and

circuit means responsive to the integrated further signal provided by said integrator for providing said common control voltage at a level which varies inversely with the level of said inteGrated further signal.

5. The circuit according to claim 4 wherein said integrator has a predetermined time constant, said circuit further comprising:

means for providing a jitter signal having a time varying amplitude with periods which are short relative to said predetermined time constant; and

means for summing said jitter signal with said integrated further signal.

6. The circuit according to claim 5 further comprising means to permit selective adjustment of said common control voltage.

7. The circuit according to claim 3 further comprising:

means for providing a jitter signal having a time-varying amplitude; and

means for summing said jitter signal with said common control voltage applied to said one-shot circuits.

8. The circuit according to claim 1 further comprising means to permit selective adjustment of said common control voltage.

9. The circuit according to claim 1 further comprising:

a threshold detector, responsive to an input data pulse train capable of assuming first, second and third levels with level transitions occurring in time-coincidence with transitions in said clock pulse train, for providing said binary data pulse train alternating between a first voltage which is present when said input data pulse train is at said first level and a second voltage which is present when said input data pulse train is at said second and third levels.