SCR memory cell

• US 3,918,033 A
• Filed: 11/11/1974
• Issued: 11/04/1975
• Est. Priority Date: 11/11/1974
• Status: Expired due to Term

• Current Assignee: David E. Norton, Donald L. Millican, Jerry R. Case
• Original Assignee: David E. Norton, Donald L. Millican, Jerry R. Case
• Inventors: Norton, David E., Case, Jerry R., Millican, Donald L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/522,659
• Time in Patent Office: 358 Days
• Field of Search: 340/173R 307/238,317R,284
• US Class Current: 365/180
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: H03K 3/352 the devices being thyristors

Abstract

A bistable memory cell (stores one binary digit or bit) suitable for semiconductive memories includes a single SCR and a single transistor plus unique interconnections to provide a read-whilewrite array of such cells. The cell topology provides a small cell size with low stand-by power. The SCR provides a memory function, while the single transistor provides an output function. In an alternative embodiment, a second transistor is employed for controlling writing into the cell.

Claims

1. A two-state memory circuit, including in combination:

a semiconductive thyratron circuit element having four semiconductive zones of alternating opposite semiconductive conductivity;

a first one zone being an anode output zone of said semiconductive thyratron circuit element;

two of said zones being control zones, and a fourth one of said zones being a cathode output zone of said semiconductive thyratron circuit element;

power supply terminal means connected to one of said output zones;

an output transistor element having collector, base control, and emitter control portions;

a first one of said control portions being connected to a given one of said output zones;

a resistive circuit element ohmically connecting one of said control zones to said cathode output zone;

read select means electrically connected to a second one of said control portions;

sense output means electrically connected to said collector portion;

write select means electrically connected to said cathode output zone; and

bit input means electrically connected to one of said zones other than said anode output zone.

2. The two-state memory circuit set forth in claim 1 wherein said cathode output zones have first and second cathode connection means;

said first cathode connection means being connected to said write select means and said resistive element; and

said second cathode connection means being connected to said bit input means.

3. The two-state memory circuit set forth in claim 2 wherein:

said base control portion being said first control portion and being ohmically connected to said anode output zone; and

a power supply resistive element being electrically interposed between said anode output zone and said power supply terminal means.

4. The two-state memory circuit set forth in claim 2 further including a Schottky barrier diode in said sense output means and having a cathode portion ohmically connected to said collector portion and having an anode portion as an output connection for said two-state memory circuit.

5. The two-state memory cell set forth in claim 2 wherein said base control portion is said first control portion and being ohmically connected to said first cathode connection means.

6. The two-state memory cell set forth in claim 2 further including second resistive means electrically interposed between said emitter portion and said read select means, and third resistive means electrically interposed between said first cathode connection means and said write select means.

7. The two-state memory circuit set forth in claim 1 wherein said bit input means includes a second transistor element having collector, base control, and emitter control segments;

said collector segment ohmically connected to one of said control zones;

one of said control segments being ohmically connected to said cathode output zone; and

a second one of said control segments being an input bit signal receiving circuit element.

8. A two-state memory circuit adapted for use in an array of such memory circuits including in combination:

A semiconductive thyratron element having a plurality greater than three of semiconductive zones of alternating and opposite semiconductive conductivity type, one of said zones being an anode end zone and another of said zones being a cathode end zone, and all other zones being intermediate to said end zones and being control zones;

an output transistor element having collector, emitter control, and base control portions;

the improvement including in combination;

a first one of said control portions being ohmically connected to a first one of said end zones;

power supply means electrically connected to a given one of said end zones;

a first select input conductor electrically connected to a second one of said coNtrol portions;

an output conductor electrically connected to said collector portion;

a second input conductor electrically connected to another of said end zones; and

a second select conductor connection electrically connected to said another of said end zones, said other electrical end zone connections to said terminal being electrically independent.

9. The two-state memory circuit set forth in claim 8 further including an input transistor element having collector, base, and emitter segments, said collector segment being ohmically connected to one of said control zones, said emitter segment and said base segment being electrically interposed between said second input conductor and said cathode end zone such that said emitter segment is ohmically connected to said second input conductor and said base segment being ohmically connected to said cathode end zone.

10. The two-state memory set forth in claim 9 further including in combination:

said anode end zone being ohmically connected to said base portion and to said resistive element;

a Schottky barrier diode electrically interposed between said collector portion and said output conductor with the cathode end of said Schottky barrier diode being ohmically connected to said collector portion;

said first select input conductor being ohmically connected to said emitter control portion, said emitter control portion being said second one of said control portions;

said second select input conductor being ohmically connected to said cathode end zone; and

a second resistive element electrically and ohmically interconnecting said cathode end zone with a first one of said other zones, said first one of said other zones being contiguous with and electrically interactive with said cathode end zone.

11. The two-state memory circuit set forth in claim 8 further including in combination:

said anode end zone being said one end zone and said given one end zone; and

said cathode end zone having first and second electrically independent connection means, one of which is electrically connected to said second input conductor and a second one of which is electrically connected to said second select input conductor.

12. The two-state memory circuit set forth in claim 8 further including in combination:

said anode end zone being connected to said power supply means and being said given one of said end zones;

said cathode end zone ohmically connected to said first one of said control portions and being said first one of said end zones; and

a resistive element ohmically interposed between one of said control zones and said one control portion.

13. The two-state memory circuit set forth in claim 8 further including in combination:

said first one of said control portions being ohmically connected to said cathode zone;

electrically resistive means electrically interposed between said cathode zone and said power supply means and said cathode zone being said given one of said end zones;

said anode end zone being said another end zone and having independent electrical connection thereto; and

a resistive element electrically interposed between one of said control zones and said second select input conductor.

14. The two-state memory circuit set forth in claim 8 wherein said semiconductive thyratron element consists of a plurality of transistor elements, said elements comprising:

a first transistor element having collector and emitter of a first electrical conductivity type separated by a base of second and opposite electrical conductivity type semiconductive material;

a second transistor element having collector and emitter consisting of said second electrical conductivity type material separated by a base consisting of said first electrical conductivity type semiconductive material;

said first transistor element emitter being said anode end zone;

said second transistor element emitter being said cathode end zone; and

means independently ohmically electrically connecting said base and collectors of said first and second transistor elements exhibiting like type semiconductive conductivities.

15. The two-state memory circuit set forth in claim 14 further including a third transistor element in said plurality of transistor elements and having a collector and emitter consisting of said second semiconductive type material separated by a base consisting of said first electrical conductivity type semiconductive material;

said base and collector of said third transistor element being independently and respectively ohmically connected to base and collector of said first and second transistor elements having the same semiconductive type material; and

the emitter of said third transistor element being connected to said second input conductor and said emitter of said first transistor element being ohmically connected to said second select input conductor.

16. A two-state memory cell for use in an array of memory cells and including a thyristor type semiconductive element having anode and cathode end zones of opposite electrical semiconductive conductivity and two control zones of opposite semiconductive conductivities interposed between said end zones such that electrically adjacent zones have opposite semiconductive conductivities;

a transistor element having collector, base control, and emitter control portions;

an ohmic connection from said anode end zone to said base control portion;

said cathode end zone having first and second electrically independent connection means;

a resistive element electrically connecting said first connection means to one of said control zones electrically adjacent said cathode end zone;

a power supply terminal means;

a second resistive element electrically connecting said terminal means to said anode end zone;

input bit terminal means ohmically connected to said second connection means;

write select terminal means ohmically connected to said first connection means;

read select terminal means ohmically connected to said emitter control portion;

a Schottkey barrier diode element having a cathode end ohmically connected to said collector portion and an anode end; and

cell output terminal means ohmically connected to said anode end.

17. The two-state memory cell set forth in claim 16 wherein said thyristor semiconductor element consists of a plurality of ohmically interconnected transistor elements and comprising:

a first transistor element having a collector and emitter of first semiconductive conductivity type material separated by a base of second and opposite semiconductive conductivity type material;

a second transistor element having a collector and emitter of said second conductivity type material separated by a base of said first conductivity type material;

said first transistor element emitter being said anode end zone;

said second transistor element emitter being said cathode end zone;

said first transistor element base being ohmically connected to said second transistor element collector and said first transistor element base ohmically connected with said second transistor element emitter being a first one of said control zones;

said first transistor element collector being ohmically connected to said second transistor element base, said first transistor element collector ohmically connected with said second transistor element base being a second one of said control zones; and

said second transistor element emitter being said cathode end zone.

18. The two-state memory cell set forth in claim 17 further including a third transistor element in said plurality of transistor elements and having a collector and emitter of said second conductivity type material separated by a base of said first conductivity type material;

said third transistor element collector being ohmically connected to said first transistor element base;

saiD third transistor element base being ohmically connected to said first transistor element collector; and

said third transistor element emitter and said second transistor element emitter jointly being said cathode end zone, and said first and second connection means being ohmically associated with said second and third transistor element emitters, respectively.