Dynamic two device memory cell which provides D.C. sense signals

• US 3,919,569 A
• Filed: 12/29/1972
• Issued: 11/11/1975
• Est. Priority Date: 12/29/1972
• Status: Expired due to Term

• Current Assignee: Fritz H. Gaensslen, Paul J. Krick
• Original Assignee: Fritz H. Gaensslen, Paul J. Krick
• Inventors: Gaensslen, Fritz H., Krick, Paul J.
• Primary Examiner(s): James, Andrew J.
• Application Number:
  US05/319,402
• Time in Patent Office: 1,047 Days
• Field of Search: 317/235B,235G 307/238,251,304,279 340/173CA
• US Class Current: 327/208
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A semiconductor two device memory cell is disclosed in which the two devices are complementary. The cell is best implemented in the integrated circuit environment and may be fabricated using well known non-complementary fabrication techniques. The cell incorporates a floating region or substrate - within - a substrate on which charge is stored in different amounts to achieve different potentials on the region thereby controlling, in one mode, the threshold of a field effect transistor of which the floating region forms a part. In a different mode, the floating region or substrate forms a drain or source region for a switching transistor which is formed in its own substrate. The latter substrate, which is formed from a semiconductor chip or wafer, besides forming the channel region of the switching transistor acts as a source for a sensing transistor which is formed by a region of opposite conductivity type in the floating region, the floating region and the substrate itself. The floating region is charged to one of two potentials when the floating region is a drain or source of the switching transistor and, the amount of current flow is controlled by the potential on the floating region when it operates as the substrate for the sensing transistor.

Claims

1. A semiconductor memory cell comprising:

a first substrate of a first field effect transistor of one semiconductor conductivity type, a second substrate of a second field effect transistor of second semiconductor conductivity type formed in said first substrate, a region of said second conductivity type disposed in said first substrate, a region of said one conductivity type disposed in said second substrate, and means electrically connected to said region of second conductivity type, and said first and second substrates for applying at least first and second potentials to said second substrate to adjust the threshold of said second FET to at least two different values.

2. A semiconductor memory cell according to claim 1 further including:

means electrically connected to said first and second substrates and said region of said one conductivity for controlling the flow of current between said region of said one conductivity type and said first substrate.

3. A semiconductor memory cell according to claim 1 wherein said one and said second semiconductor conductivity types are n and p, respectively.

4. A semiconductor memory cell according to claim 1 wherein said one and said second semiconductor conductivity type are p and n, respectively.

5. A semiconductor memory cell according to claim 1 wherein said means for applying at least first and second potentials to adjust the threshold of said second field effect transistor includes a first pulsed source connected to said region of said second conductivity type, a conductor disposed in insulated spaced relationship with said first and second substrates and said regions having a portion disposed in electric field coupled relationship with said second substrate and with a portion of said first substrate which is disposed between said second substrate and said region of said second conductivity type and a second pulsed source connected to said conductor, the activation of at least one of said sources being sufficient to apply a potential to said second substrate.

6. A semiconductor cell according to claim 2 wherein said means for controlling the flow of current includes a pulsed source connected to said region of said one conductivity, a conductor disposed in insulated spaced relationship with said first and second substrates and said regions having at least a portion thereof disposed in electric field coupled relationship with said second substrate and a second pulsed source connected to said conductor, the simultaneous activation of said sources controlling the flow of current between said region of said one conductivity type and said first substrate.

7. A semiconductor device according to claim 6 wherein the second pulsed source when activated has an amplitude insufficient to overcome one of said at least two different values of threshold voltage.