Phase-locked frequency synthesizer with means for restoring stability

• US 3,921,094 A
• Filed: 10/07/1974
• Issued: 11/18/1975
• Est. Priority Date: 10/07/1974
• Status: Expired due to Term

• Current Assignee: Clifford Warren Schaible
• Original Assignee: Clifford Warren Schaible
• Inventors: Schaible, Clifford Warren
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US05/512,537
• Time in Patent Office: 407 Days
• Field of Search: 331/1A,8,10,17,18,25
• US Class Current: 331/1.00A
• CPC Class Codes: H03L 7/185 using a mixer in the loop H03L7/187 - H03L7/195 take precedence

Abstract

A cellular type high capacity mobile communication system requires a large number of channels for use on a selective basis within each of several small cells. In the system described, switching from one channel to another to avoid interference within the new cell is accomplished as the mobile communicator moves from one cell to another. Both the base station within each cell and the mobile units require the means for generating the necessary frequencies and for pulling in the frequency of the transmitter or receiver of the base station and the mobile unit rapidly and stabilizing it at the new frequency. In this frequency synthesizer, phase-locked loop instability resulting from over-leaping intermediate channel frequencies is overcome by detecting, ahead of the frequency and phase comparator, the absence of an output from the frequency countdown circuitry of the feedback portion of the phase-locked loop. The signal that is representative of the absence of the normal feedback signal or its complete lack is applied to a transistor circuit that biases the voltage-controlled oscillator to the midpoint of its range and that has such a low output impedance that it '"'"''"'"''"'"''"'"'swamps out'"'"''"'"''"'"''"'"' the relatively high output impedance of the feedback path after the comparator. As a stable feedback signal is restored so that a detectable frequency countdown signal is obtained, the transistorized circuit is disconnected. The mode of operation of this transistorized circuit is somewhat analogous to circuits commonly called crowbar circuits.

Claims

1. A frequency synthesizer of the type in which a voltagecontrolled oscillator is disposed in a phase-locked loop including a phase and frequency comparator adapted to receive an external reference signal and a feedback signal to generate an error signal, means for applying the error signal to the control circuit of the voltage-controlled oscillator, means for deriving the feedback signal from the output signal generated by the voltage-controlled oscillator, and in which means are provided for altering the loop to facilitate frequency pull-in under some conditions of operation, characterized in that the deriving means includes frequency-count-down circuit means for deriving the feedback signal, said circuit means generating a substantially zero feedback signal when its frequency-response range is exceeded, and in that the loop altering means comprises semiconductive switching means for effectively disabling the loop between the output of the comparator and the voltage-controlled oscillator and for resetting the oscillator to a midpoint of its frequency range when the circuit means generates a substantially zero feedback signal.

2. A frequency synthesizer of the type claimed in claim 1 in which the semiconductive switching means includes an input circuit comprising monostable multivibrator means connected to the frequency-count-down circuit means for providing longer pulses than the frequency-count-down circuit means.

3. A frequency synthesizer of the type claimed in claim 2 in which the semiconductive switching means comprises a series voltage-dividing circuit including a source of reference potential, a resistance, at least one semiconductive junction, said series circuit being connected in series with the control circuit of the voltage-controlled oscillator, said semiconducting switching means including semiconductive driving circuit means coupled between the output of the monostable multivibrator means and said one semiconductive junction for causing said junction to conduct when the pulses from the multivibrator means are absent for a selected period of time, whereupon the series circuit supplies a fixed potential to the control circuit of the voltage controlled oscillator to reset the oscillator.

4. A frequency synthesizer of the type in which a voltage-controlled oscillator is disposed in a phase-locked loop including a phase and frequency comparator adapted to receive an external reference signal and a feedback signal to generate an error signal, means including a low-pass filter for applying the error signal to the control circuit of the voltage-controlled oscillator, means for deriving the feedback signal from the output signal generated by the voltage-controlled oscillator, and in which means are provided for altering the loop to facilitate frequency pull-in under some conditions of operation, characterized in that the deriving means includes frequency-count-down circuit means for deriving the feedback signal, said circuit means generating a substantially zero feedback signal when its frequency-response range is exceeded, and further characterized in that the loop altering means comprises semiconductive switching means for shunting the loop path between the low-pass filter and the control circuit of the voltage controlled oscillator, and having an input coupled to the output of the frequency-count-down circuit means to load down the loop when said frequency-count-down circuit means generates a negligible feedback signal and to apply a fixed potential to said control circuit, thereby resetTing the oscillator to a midpoint of its frequency range.

5. A frequency synthesizer of the type claimed in claim 4 in which the semiconductive switching means includes a monostable multivibrator circuit adapted to produce longer control pulses than those generated by the frequency-count-down circuit means, to delay the loading down of the loop for a selected time after the signal from the frequency-count-down circuit has become negligible and to delay removal of the loading down for a second selected period of time after the signal from the frequency-count-down circuit has ceased to be negligible.