Capacitance matrix keyboard

• US 3,921,166 A
• Filed: 09/15/1972
• Issued: 11/18/1975
• Est. Priority Date: 09/15/1972
• Status: Expired due to Term

• Current Assignee: John W. Volpe
• Original Assignee: John W. Volpe
• Inventors: Volpe, John W.
• Primary Examiner(s): Habecker, Thomas B.
• Application Number:
  US05/289,523
• Time in Patent Office: 1,159 Days
• Field of Search: 340/365C,365E,365S,146.1AB
• US Class Current: 341/26
• CPC Class Codes: H03K 17/98 having a plurality of control members, e.g. keyboard
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence
• CPC Class Codes: H04L 17/02 Apparatus or circuits at the transmitting end
• CPC Class Codes: H04L 17/04 with keyboard co-operating with code-bars

Abstract

An electronic system having a keyboard for entry of digitally coded data on a carrier wherein capacitive switches operated by the keyboard program a matrix which is scanned to produce digitally coded data trains.

Claims

1. In combination:

a matrix of capacitive key switches, said matrix having first and second sets of conductors;

means for providing a count;

means for providing a carrier signal;

means for applying said carrier signal to said first set of conductors one at a time in response to said count providing means; and

means for detecting the conductor of said first set of conductors to which said carrier signal is applied and to which conductor of said second set of conductors and carrier signal is coupled by a selected one of said key switches.

2. The combination as set forth in claim 1 wherein said key switches comprise:

first and second stationary plates and a movable plate, said first stationary plate being coupled to a conductor of said first set of conductors and said second stationary plate being coupled to a conductor of said second set of conductors.

3. ThE combination as set forth in claim 1 wherein said detecting means comprises:

means to selectively couple said second set of conductors one at a time to demodulator means in response to said count providing means;

means to demodulate said carrier signal; and

means to generate a first output state when the said carrier signal is present and a second output state when the said carrier signal is not present.

4. The combination as set forth in claim 3 wherein said detecting means further comprises:

means to store the count from said count providing means; and

means to prevent said count from being stored more than once for each selection of a key switch.

5. The combination of claim 4 further comprising means for coupling said means to store said count to data processing means.

6. The combination as set forth in claim 1 wherein said means for applying said carrier signal to each conductor of the said first set of conductors comprises:

means to convert from a binary code to a single activated line unique to each binary code number wherein said carrier signal is connected as the most significant bit of said binary code.

7. A keyboard comprising in combination:

means to produce a continuously cycling binary count;

a carrier signal source;

means for applying said carrier signal to a first set of conductors one at a time in response to the higher order bits of said binary count;

means to selectively couple said carrier signal from a conductor of said first set of conductors to a conductor of a second set of conductors;

means to couple in response to the lower order bits of said binary count said second set of conductors one at a time to a demodulator means;

means to demodulate said carrier signal; and

means to store the said binary count.

8. The combination as set forth in claim 7 wherein shift register means is connected to the output of said demodulator, said shift register means having the same delay time as the time required for a complete cycle of said means to produce a continuously cycling binary count such that the output of the shift register cooperates with the output of the said demodulator so as to prevent the count corresponding to a key switch from being stored more than once each time that key switch is depressed.

9. The combination as set forth in claim 7 wherein said means for applying said carrier signal comprises:

a binary decoder to convert from a binary code to a single activated output line; and

a carrier signal source, said signal source connected to said decoder as the most significant bit of the binary code.

10. The combination as set forth in claim 7 wherein said means to couple said carrier signal comprises a capacitive key switch.

11. The combination as set forth in claim 7 wherein said means to couple said second set of conductors one at a time to a demodulator comprises a multiplexer means with a plurality of data inputs and a single data output.

12. A keyboard comprising in combination:

a six-bit continuously cycling binary counter;

a four line to ten line binary coded decimal-to-decimal decoder/driver, said decoder/driver having the three least significant bits of its input connected to the three most significant bits of the said binary counter;

a first set of eight conductors connected to the zeroth through the seventh outputs of said decoder/driver;

a second set of eight conductors;

a plurality of capacitive key switches, said capacitive key switches having first and second terminals, said first terminal of each of said capacitive key switches connected to one conductor within said first set of conductors and said second terminal of each of said capacitive key switches connected to one conductor within said second set of conductors;

means to amplify the signals on each of the said second set of conductors;

an eight input digital data multiplexer, the outputs of said amplifying means connected to the datA inputs of said multiplexer and the three least significant bits of said binary counter connected to the data selection inputs of said multiplexer;

demodulator means, the input of said demodulator means connected to the output of said multiplexer means;

a 64-bit shift register, the clock input of said shift register being connected to the same clock source as the said six-bit continuously cycling binary counter and the data input of said shift register means being connected to the output of said demodulator;

an output storage means having a plurality of data inputs and outputs and a single clock input, some of the data inputs of said output storage means connected to the outputs of the said six-bit continuously cycling binary counter; and

gating means, one or more of the inputs of said gating means connected to the output of said shift register, one or more of the inputs of said gating means connected to the output of said demodulator, one or more inputs connected to the same clock source as the said six-bit continuously cycling binary counter, and the output of said gating means connected to the clock input of said output storage means.