Coherent, fixed BAUD rate FSK communication method and apparatus
First Claim
1. A frequency shift key (FSK) communication apparatus for communicating time division binary message codes comprising a predetermined number of message bits, having logic levels representing logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"', from a transmitter station to a receiver station, the apparatus comprising:
- a digital encoder in the transmitter station, having a predetermined message code comprising a predetermined number (N) message bits, generating at least two output signal levels for each message bit of the N-bit message code at a digital encoder output signal;
an FSK generator in the transmitter station receiving the digital encoder output signal and providing an output signal having a distinct frequency in response to each received digital encoder output signal level, the FSK generator output signal having a fixed transmission time for the (N) bit message code independent of the number of logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"' comprising the (N) bit message code;
means in the transmitter station receiving the FSK generator output signal and providing a transmitter master clock signal derived from the received FSK generator output signal and having a frequency coherently related to the FSK generator output signal frequency, the transmitted master clock signal being connected to the digital encoder and operating the digital encoder to provide the digital encoder output signal in one condition of the digital encoder;
means in the transmitter station receiving and transmitting the FSK generator output signal;
means in the receiver station receiving the transmitted FSK generator output signal and providing an output signal corresponding to the received FSK generator output signal;
means in the receiver station receiving the output signal corresponding to the transmitted FSK generator output signal and providing a receiver master clock signal derived from the received FSK generator output signal and having a frequency coherently related to the FSK generator output signal frequency; and
means in the receiver station receiving the receiver master clock signal, receiving the output signal corresponding to the transmitted FSK generator output signal and decoding the transmitted FSK generator output signal to derive the transmitted message code, the receiveR master clock signal providing the receiver master clock signal pulses for decoding the transmitted FSK generator output signal at a frequency coherently related to the frequency of the transmitter master clock signal.
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Abstract
An improved FSK communication method and apparatus for communicating time division binary codes wherein the complement of each message bit is generated and transmitted following the generation and transmission of the message bit and wherein the transmitter and the receiver master clock signals are each derived from the FSK generator output signal, the transmission time for a message bit of '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' being the same as the transmission time for a message bit of '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' thereby providing a frequency coherent FSK communication system having a fixed BAUD rate for message transmission independent of the number of '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"' and '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' comprising the communicated message code. A synchronization signal is automatically produced prior to the generation of the message bits and the message bit complements, and the messagae code is automatically repeated a predetermined number of times.
80 Citations
43 Claims
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1. A frequency shift key (FSK) communication apparatus for communicating time division binary message codes comprising a predetermined number of message bits, having logic levels representing logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"', from a transmitter station to a receiver station, the apparatus comprising:
- a digital encoder in the transmitter station, having a predetermined message code comprising a predetermined number (N) message bits, generating at least two output signal levels for each message bit of the N-bit message code at a digital encoder output signal;
an FSK generator in the transmitter station receiving the digital encoder output signal and providing an output signal having a distinct frequency in response to each received digital encoder output signal level, the FSK generator output signal having a fixed transmission time for the (N) bit message code independent of the number of logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"' comprising the (N) bit message code;
means in the transmitter station receiving the FSK generator output signal and providing a transmitter master clock signal derived from the received FSK generator output signal and having a frequency coherently related to the FSK generator output signal frequency, the transmitted master clock signal being connected to the digital encoder and operating the digital encoder to provide the digital encoder output signal in one condition of the digital encoder;
means in the transmitter station receiving and transmitting the FSK generator output signal;
means in the receiver station receiving the transmitted FSK generator output signal and providing an output signal corresponding to the received FSK generator output signal;
means in the receiver station receiving the output signal corresponding to the transmitted FSK generator output signal and providing a receiver master clock signal derived from the received FSK generator output signal and having a frequency coherently related to the FSK generator output signal frequency; and
means in the receiver station receiving the receiver master clock signal, receiving the output signal corresponding to the transmitted FSK generator output signal and decoding the transmitted FSK generator output signal to derive the transmitted message code, the receiveR master clock signal providing the receiver master clock signal pulses for decoding the transmitted FSK generator output signal at a frequency coherently related to the frequency of the transmitter master clock signal.
- a digital encoder in the transmitter station, having a predetermined message code comprising a predetermined number (N) message bits, generating at least two output signal levels for each message bit of the N-bit message code at a digital encoder output signal;
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2. The apparatus of claim 1 wherein the means in the transmitter station receiving and transmitting the FSK generator output signal is defined further to include:
- a transmitter modulator in the transmitter station, having an activated condition, receiving the FSK generator output signal and providing an output signal in the activated condition thereof; and
a transmitter generator a carrier signal and receiving the transmitter modulator output signal, the carrier signal being modulated via the FSK generator output signal provided via the transmitter modulator output signal; and
wherein the means in the receiver station receiving the transmitted FSK generator output signal is defined further to include;
a receiver receiving the transmitted carrier signal modulated via the FSK generator output signal and providing the FSK generator output signal via the output signal therefrom; and
wherein the means in the receiver station decoding the transmitted FSK generator output signal is defined further to include;
an FSK demodulator receiving the receiver output signal and providing a time division binary coded output signal in response thereto, the FSK demodulator output signal corresponding to the digital encoder output signal; and
a digital decoder receiving the receiver master clock signal, the FSK demodulator output signal and decoding the FSK demodulator output signal to derive the transmitted message code.
- a transmitter modulator in the transmitter station, having an activated condition, receiving the FSK generator output signal and providing an output signal in the activated condition thereof; and
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3. The apparatus of claim 2 defined further to include:
- a comparison network in the receiver station, having a receiver code encoded therein, connected to the digital decoder, the comparison network receiving the derived transmitted message code, comparing the transmitted message code with the receiver code and providing comparison signal in response to an identical comparison of the receiver code and the transmitted message code.
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4. The apparatus of claim 1 wherein the digital encoder is defined further as generating the message bit followed by the message bit complement for each message bit of the (N) bit message code;
- and wherein the FSK generator provides an output signal having the frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' and then provides an output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' for each message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' in the (N) bit message code, and provides the output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' and then provides the output signal having the frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' for each message bit of the (N) bit message code of logical '"'"''"'"''"'"''"'"'one.'"'"''"'"''"'"''"'"'
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5. The apparatus of claim 1 wherein the means providing the transmitter master clock signal is defined further to include:
- a P-counter receiving the FSK generator output signal and providing a transmitter master clock signal pulse in response to each predetermined number (P) cycles of the received FSK generator output signal; and
wherein the means providing the receiver master clock signal is defined further to include;
a P-counter receiving the output signal corresponding to the transmitted FSK generator output signal and providing a receiver master clock pulse in response to each predetermined number (P) cycles of the received output signal corresponding to the FSK generator output signal.
- a P-counter receiving the FSK generator output signal and providing a transmitter master clock signal pulse in response to each predetermined number (P) cycles of the received FSK generator output signal; and
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6. The apparatus of claim 1 wherein the digital encoder is defined further to include:
- means receiving the transmitter master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the transmitter master clock signal frequency;
an N-bit shift register receiving the shift register clock signal, having a portion for receiving an N-bit message code and providing an output signal, each message bit of the N-bit message code received via the N-bit shift register being clocked from the N-bit shift register in a serial manner in response to the received shift register clock signal pulses;
means connected to the N-bit shift register for providing the N-bit message code to the N-bit shift register in one condition; and
means receiving the N-bit shift register output signal, having a portion generating a message bit complement for each message bit clocked from the N-bit shift register and providing the message bit followed by the message bit complement for each message bit of the (N) bit message code in a serial manner via an output signal, said last-mentioned output signal being the digital encoder output signal.
- means receiving the transmitter master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the transmitter master clock signal frequency;
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7. The apparatus of claim 6 wherein the FSK generator is defined further as providing an output signal having a frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' and then providing the output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' for each message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' in the (N) bit message code, and providing the output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' and then providing the output signal having the frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' for each message bit of the (N) bit message code of logical '"'"''"'"''"'"''"'"'one.'"'"''"'"''"'"''"'"'
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8. The apparatus of claim 6 wherein the means in the receiver station decoding the transmitted FSK generator output signal is defined further to include:
- an FSK demodulator receiving the signal corresponding to the FSK generator output signal and providing a time divisison binary coded output signal in response thereto, the FSK demodulator output signal corresponding to the digital encoder output signal; and
a digital decoder, comprising;
means receiving the receiver master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the receiver master clock signal frequency;
an N-bit shift register, having one portion for receiving the shift register clock signal and another portion for receiving message bits, a message bit being clocked into the N-bit shift register in a serial manner when receiving a message bit and a shift register clock signal pulse; and
means receiving the FSK demodulator output signal and providing an output signal connecting each message bit provided via the FSK demodulator output signal to the N-bit shift register, the message bits being clocked into the N-bit shift register via the shift register clock signal.
- an FSK demodulator receiving the signal corresponding to the FSK generator output signal and providing a time divisison binary coded output signal in response thereto, the FSK demodulator output signal corresponding to the digital encoder output signal; and
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9. The apparatus of claim 8 wherein the means connecting each message bit to the N-bit shift register is defined further to include:
- means receiving the FSK demodulator output signal, comparing each message bit received via the FSK demodulator output signal with the following data bit received via the FSK demodulator output signal, and providing a high output signal in response to each received message bit when followed by the message bit complement and providing a low output signal in response to each received message bit followed by a data bit other than the message bit complement of the preceding message bit; and
means receiving the shift register clock signal, receiving the output signal from the means comparing each message bit received via the FSK demodulator output signal with the next received data bit, and providing the shift register clock signal to the N-bit shift register in response to a received high output signal from the means comparing each message bit with the next received data bit, thereby clocking the message bit into the N-bit shift register.
- means receiving the FSK demodulator output signal, comparing each message bit received via the FSK demodulator output signal with the following data bit received via the FSK demodulator output signal, and providing a high output signal in response to each received message bit when followed by the message bit complement and providing a low output signal in response to each received message bit followed by a data bit other than the message bit complement of the preceding message bit; and
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10. The apparatus of claim 9 wherein the means comparing each message bit with the following code bit is defined further to include:
- a 1-bit shift register receiving the FSK demodulator output signal, each received data bit being clocked into the 1-bit shift register when receiving a 1-bit shift register clock signal pulse, and providing the received data bit via an output signal connected to the N-bit shift register;
means receiving the receiver master clock signal and providing a 1-bit shift register clock signal, the 1-bit shift register clock signal being connected to the 1-bit shift register for clocking only the received message bits into the 1-bit shift register, each message bit clocked into the 1-bit shift register being provided via the 1-bit shift register output signal; and
gate means receiving the 1-bit shift register output signal and the FSK demodulator output signal, providing a high output signal when receiving a message bit via the 1-bit shift register output signal and the complement of the message bit on the 1-bit shift register output signal via the FSK demodulator output signal, and providing a low output signal when receiving a message bit via the 1-bit shift register output signal and a data bit other than the complement of the message bit on the 1-bit shift register output signal via the FSK demodulator output signal; and
wherein the means providing the shift register clock signal to the N-bit shift register in response to a received high output signal is defined further as receiving the shift register clock signal and the gate means output signal, the message bit provided via the one-bit shift register output signal being clocked into the N-bit shift register via the shift register clock signal in the high condition of the gate means output signal.
- a 1-bit shift register receiving the FSK demodulator output signal, each received data bit being clocked into the 1-bit shift register when receiving a 1-bit shift register clock signal pulse, and providing the received data bit via an output signal connected to the N-bit shift register;
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11. The apparatus of claim 8 defined further to include:
- means generating an output signal in response to a message bit being clocked into the N-bit shift register indicating a message bit followed by the message bit complement received via the receiver station;
an N-counter receiving the output signal generated in response to a message bit being clocked into the N-bit shift register and providing an output signal in response to a predetermined number (N) received signals indicating a predetermined number (N) message bits clocked into the N-bit shift register; and
an M-counter receiving the N-counter output signal and providing a valid data signal in response to a received predetermined number (M) N-counter output signal pulses indicating the predetermined number (N) message bits clocked into the N-bit shift register a predetermined number (M) times.
- means generating an output signal in response to a message bit being clocked into the N-bit shift register indicating a message bit followed by the message bit complement received via the receiver station;
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12. The apparatus of claim 11 wherein the digital encoder is defined further to include:
- means producing a synchronization signal prior to the generation of each of the message bits followed by the message bit complement for the (N) bit message code, the synchronization signal being provided via the digital encoder output signal; and
wherein the digital decoder is defined further to include;
means connected to the N-counter producing a reset signal in respoNse to a received synchronization signal resetting, the reset signal being connected to and resetting the N-counter.
- means producing a synchronization signal prior to the generation of each of the message bits followed by the message bit complement for the (N) bit message code, the synchronization signal being provided via the digital encoder output signal; and
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13. The apparatus of claim 6 wherein the means providing the message bit followed by the message bit complement for each message bit of the (N) bit message code is further defined as providing the message bit during a half cycle of the shift register clock signal pulse and the message bit complement during the next half cycle of the shift register clock signal pulse in a serial manner for each message bit of the (N) bit message code.
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14. The apparatus of claim 13 wherein the means providing the message bit followed by the message bit complement is defined further to include a portion producing the first message bit of the (N) bit message code during the first half cycle of the shift register clock signal and during the next half cycle of the shift register clock signal immediately prior to producing the message bit and message bit complement sequence in a serial manner for each message bit of the (N) bit message code, the signal produced during the first half cycle and the next half cycle of the shift register clock signal providing a synchronization signal.
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15. The apparatus of claim 6 wherein the means generating the message bits and the message bit complements is defined further to include:
- gate means receiving the shift register clock signal and the N-bit shift register output signal providing an output signal having a logic level corresponding to the message bit logic level on the N-bit shift register output signal when receiving a shift register clock signal in the high state;
an inverter receiving the shift register clock signal and providing an output signal in the high state in response to a received shift register clock signal in the low state and providing an output signal in the low state in response to a received shift register clock signal in the high state;
an inverter receiving the N-bit shift register output signal and providing an output signal in the high state in response to a received N-bit shift register output signal in the low state and providing an output signal in the low state in response to a received N-bit shift register output signal in the high state;
gate means receiving the first-mentioned inverter output signal and receiving the second-mentioned inverter output signal and providing an output signal having a logic level corresponding to the complement of the message bit on the N-bit shift register output signal in a low state of the shift register clock signal; and
means receiving the first-mentioned gate means output signal and receiving the last-mentioned gate means output signal and providing the digital encoder output signal having a logic level corresponding to the message bit clocked from the N-bit shift register in the high state of the shift register clock signal and providing the digital encoder output signal having a logic level corresponding to the complement of the message bit clocked from the N-bit shift register in the low state of the shift register clock signal.
- gate means receiving the shift register clock signal and the N-bit shift register output signal providing an output signal having a logic level corresponding to the message bit logic level on the N-bit shift register output signal when receiving a shift register clock signal in the high state;
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16. The apparatus of claim 15 wherein the means providing the transmitter shift register clock signal includes:
- a counter receiving the transmitter master clock signal and providing the shift register clock signal having a frequency of one-half the frequency of the received transmitter master clock signal, the message bit being provided during a half cycle of the shift register clock signal in the high state of the shift register clock signal and the complement of the preceding message bit being provided during the next half cycle of the shift register clock signal in the low state of the shift register clock signal.
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17. The apparatus of claim 15 wherein the transmitter N-bit shift register output signal is connected to the input of the N-bit shift register, the message bit clocked from the N-bit shift register being clocked back into the N-bit shift register and the Message bits of the N-bit message code being provided cyclically via the N-bit shift register output signal.
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18. The apparatus of claim 17 wherein the means transmitting the FSK generator output signal has an operative and an inoperative condition, said means transmitting the FSK generator output signal in the operative condition thereof;
- and wherein the apparatus is defined further to include;
an M-counter connected to the digital encoder and the means transmitting the FSK generator output signal, the M-counter providing an output signal in the high state connected to the means transmitting the FSK generator output signal and rendering the means transmitting the FSK generator output signal inoperative in response to the N-bit message code being repeated a predetermined number (M) times, the M-counter output signal being returned to the low state in a predetermined period of time corresponding to the time required to repeat the N-bit message code the predetermined number (M) times.
- and wherein the apparatus is defined further to include;
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19. The apparatus of claim 15 defined further to include:
- first counter means receiving the shift register clock signal and counting the number of message bits clocked from the N-bit shift register in an activated condition of the first counter means, the first counter means producing an output signal in the high state in response to the predetermined number (N) message bits being clocked from the N-bit shift register;
gate means receiving the transmitter master clock signal and the first counter means output signal, the gate means providing the transmitter master clock signal in the low state of the received first counter means output signal and inhibiting the transmitter master clock signal in the high state of the first counter means output signal; and
second counter means receiving the transmitter master clock signal and providing an output signal in the high state in response to a received predetermined number of transmitter master clock signal pulses in an activated condition of the second counter means, the second counter means receiving the first counter means output signal and being activated in response to a received first counter means output signal in the low state, the second counter means output signal being connected to the first counter means and activating and resetting the first counter means in the low state of the second counter means output signal, the first message bit of the N-bit message code being provided via the digital encoder output signal in the high state of the second counter means and the digital encoder output produced in the high state of the second counter means being produced prior to the generation of the message bits and the message bit complements of the N-bit message code and providing a synchronization signal.
- first counter means receiving the shift register clock signal and counting the number of message bits clocked from the N-bit shift register in an activated condition of the first counter means, the first counter means producing an output signal in the high state in response to the predetermined number (N) message bits being clocked from the N-bit shift register;
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20. The apparatus of claim 16 wherein the means providing the receiver shift register clock signal includes:
- a counter receiving the receiver master clock signal and providing an output signal having a frequency of one-half the frequency of the received receiver master clock signal;
gate means receiving the counter output signal having a frequency one-half the frequency of the receiver master clock signal and receiving the receiver master clock signal and providing a 1-bit shift register clock signal pulse in the high state of the counter output signal having a frequency one-half the frequency of the receiver master clock signal and in the high state of the receiver master clock signal;
a 1-bit shift register receiving the FSK demodulator output signal and the 1-bit shift register clock signal, the data bit on the FSK demodulator output signal being clocked into the 1-bit shift register in response to a received 1-bit shift register clock signal pulse, the 1-bit shift register clock signal clocking only the message bits into the 1-bit shift register and the message bit complements being on the received FSK demodulator output signal in the low state of the 1-bit shift register clock signal, each message bit clocked into the 1-bit shift register being provided via the 1-bit shift register output signal;
gate means receiving the 1-bit shift register output signal and the FSK demodulator output signal, providing a high output signal when receiving a message bit via the 1-bit shift register output signal and the complement of the message bit on the 1-bit shift register output signal via the FSK demodulator output signal, and providing a low output signal when receiving a message bit via the 1-bit shift register output signal and a data bit other than the complement of the message bit on the 1-bit shift register output signal via the FSK demodulator output signal;
means receiving the counter output signal having a frequency of one-half of the receiver master clock signal frequency and the last-mentioned gate means output signal, and providing a shift register clock signal pulse corresponding to the counter output signal having a frequency of one-half the receiver master clock signal frequency when receiving the last-mentioned gate means output signal in the high state indicating a message bit on the 1-bit shift register output signal and the complement of the message bit on the 1-bit shift register output signal being received via the FSK demodulator output signal; and
an N-bit shift register having one portion receiving the shift register clock signal and another portion receiving the 1-bit shift register output signal, the message bit on the 1-bit shift register clock signal being clocked into the N-bit shift register when receiving a shift register clock signal pulse.
- a counter receiving the receiver master clock signal and providing an output signal having a frequency of one-half the frequency of the received receiver master clock signal;
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21. The apparatus of claim 20 wherein the means providing the shift register clock signal in the receiver includes:
- an inverter receiving the counter output signal having a frequency of one-half the frequency of the receiver master clock signal frequency, and providing an output signal in the high state in response to a received signal in the low state and providing an output signal in the low state in response to a received signal in the high state;
an AND gate receiving the inverter output signal and the receiver master clock signal, and providing the inverter output signal via an AND gate output signal in the high state of the received receiver master clock signal; and
an AND gate receiving the first-mentioned AND gate output signal and the gate means output signal having a high state indicating a received message bit followed by the complement of the received message bit, the last-mentioned gate means providing the shift register clock signal corresponding to the inverter output signal in the high state of the received gate means output signal indicating a message bit on the one-bit shift register output signal followed by the complement of the message bit.
- an inverter receiving the counter output signal having a frequency of one-half the frequency of the receiver master clock signal frequency, and providing an output signal in the high state in response to a received signal in the low state and providing an output signal in the low state in response to a received signal in the high state;
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22. The apparatus of claim 21 wherein the digital encoder is defined further to include:
- means producing a synchronization signal, having a logic level corresponding to the logic level of the first message bit of the N-bit message code and a time duration corresponding to the duration of two first message bits, the synchronization signal being produced immediately prior to producing the message bit and the message bit complement sequence; and
wherein the apparatus includes;
means in the receiver station receiving the shift register clock signal and providing an output signal pulse indicating a message bit being clocked into the N-bit shift register;
an N-counter receiving the output signal pulse indicating a message bit being clocked into the N-bit shift register and providing an output signal pulse in response to a predetermined number (N) of input signal pulses received thereby;
means receiving the gate means output signal indicating a received message bit followed by the message bit complemenT and providing an output reset signal in the high state in the low state of the received gate means output signal, the output reset signal being connected to and resetting the N-counter in the high state of the output reset signal, the N-counter being reset in response to the two received synchronization bits and in response to an error indicating a received message bit followed by a data bit other than the message bit complement; and
an M-counter receiving the N-counter output signal and providing an output valid data signal in response to a predetermined number (M) received N-counter output signal pulses indicating the (N) message bits and the (N) message bit complements received a predetermined number (M) times.
- means producing a synchronization signal, having a logic level corresponding to the logic level of the first message bit of the N-bit message code and a time duration corresponding to the duration of two first message bits, the synchronization signal being produced immediately prior to producing the message bit and the message bit complement sequence; and
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23. The apparatus of claim 22 wherein the counter providing the output signal having a frequency of one-half the frequency of the receiver master clock signal frequency is defined further as receiving the output reset signal and being reset in the high state of the output reset signal thereby inhibiting the 1-bit shift register clock signal and inhibiting the shift register clock signal until the detection of a message bit complement via the gate means providing an output signal indicating a received message bit and a received message bit complement.
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24. The apparatus of claim 23 defined further to include:
- means comparing each message bit of a received N-bit message code with the corresponding message bit of the preceding received N-bit message code and providing an output reset signal in response to a difference in the compared message bits, the output reset signal being connected to and resetting the M-counter and the N-counter thereby substantially assuring the repeatability of the received message code.
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25. A frequency shift key (FSK) communication apparatus for communicating time division binary message codes comprising a predetermined number of message bits, having logic levels representing logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros,'"'"''"'"''"'"''"'"' from a transmitter station to a receiver station, the apparatus comprising:
- a digital encoder, having a predetermined message code comprising a predetermined number (N) message bits, generating at least two output signal levels for each message bit of the N-bit message code at a digital encoder output signal;
an FSK generator receiving the digital encoder output signal and providing an output signal having a distinct frequency in response to each received digital encoder output signal level, the FSK generator output signal having a fixed transmission time for the (N) bit message code independent of the number of logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"' comprising the (N) bit message code; and
means receiving the FSK generator output signal and providing a transmitter master clock signal derived from the received FSK generator output signal and having a frequency coherently related to the FSK generator output signal frequency, the transmitter master clock signal being connected to the digital encoder and operating the digital encoder to provide the digital encoder output signal in one condition of the digital encoder.
- a digital encoder, having a predetermined message code comprising a predetermined number (N) message bits, generating at least two output signal levels for each message bit of the N-bit message code at a digital encoder output signal;
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26. The apparatus of claim 25 wherein the digital encoder is defined further as generating the message bit followed by the message bit complement for each message bit of the (N) bit message code;
- and wherein the FSK generator provides an output signal having the frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' and then provides an output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' for each message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' in the (N) bit message code, and provides the output signal having the frequency (fm) in response to a receivEd digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' and then provides the output signal having the frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' for each message bit of the (N) bit message code of logical '"'"''"'"''"'"''"'"'one.'"'"''"'"''"'"''"'"'
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27. The apparatus of claim 26 wherein the means providing the transmitter master clock signal is defined further to include:
- a P-counter receiving the FSK generator output signal and providing a transmitter master clock signal pulse in response to each predetermined number (P) cycles of the received FSK generator output signal; and
wherein the means providing the receiver master clock signal is defined further to include;
a P-counter receiving the output signal corresponding to the transmitted FSK generator output signal and providing a receiver master clock pulse in response to each predetermined number (P) cycles of the received output signal corresponding to the FSK generator output signal.
- a P-counter receiving the FSK generator output signal and providing a transmitter master clock signal pulse in response to each predetermined number (P) cycles of the received FSK generator output signal; and
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28. The apparatus of claim 25 wherein the digital encoder is defined further to include:
- means receiving the transmitter master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the transmitter master clock signal frequency;
an N-bit shift register receiving the shift register clock signal, having a portion for receiving an N-bit message code and providing an output signal, each message bit of the N-bit message code received via the N-bit shift register being clocked from the N-bit shift register in a serial manner in response to the received shift register clock signal pulses;
means connected to the N-bit shift register for providing the N-bit message code to the N-bit shift register in one condition; and
means receiving the N-bit shift register output signal, having a portion generating a message bit complement for each message bit clocked from the N-bit shift register and providing the message bit followed by the message bit complement for each message bit of the (N) bit message code in a serial manner via an output signal, said last-mentioned output signal being the digital encoder output signal.
- means receiving the transmitter master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the transmitter master clock signal frequency;
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29. The apparatus of claim 28 wherein the FSK generator is defined further as providing an output signal having a frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' and then providing the output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' for each message bit of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' in the (N) bit message code, and providing the output signal having the frequency (fm) in response to a received digital encoder output signal having a logic level representing a message bit of logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"' and then providing the output signal having the frequency (fs) in response to a received digital encoder output signal having a logic level representing a message bit complement of logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' for each message bit of the (N) bit message code of logical '"'"''"'"''"'"''"'"'one. '"'"''"'"''"'"''"'"'
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30. The apparatus of claim 28 wherein the means providing the message bit followed by the message bit complement for each message bit of the (N) bit message code is further defined as providing the message bit during a half cycle of the shift register clock signal pulse and the message bit complement during the next half cycle of the shift register clock signal pulse in a serial manner for each message bit of the (N) bit message code.
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31. The apparatus of claim 29 wherein the means providing the message bit followed by the message bit complement is defined furtHer to include a portion producing the first message bit of the (N) bit message code during the first half cycle of the shift register clock signal and during the next half cycle of the shift register clock signal immediately prior to producing the message bit and message bit complement sequence in a serial manner for each message bit of the (N) bit message code, the signal produced during the first half cycle and the next half cycle of the shift register clock signal providing a synchronization signal.
-
32. The apparatus of claim 25 wherein the digital encoder is defined further to include:
- means receiving the transmitter master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the transmitter master clock signal frequency;
an N-bit shift register receiving the shift register clock signal, having a portion for receiving an N-bit message code and providing an output signal, each message bit of the N-bit message code received via the N-bit shift register being clocked from the N-bit shift register in a serial manner in response to the received shift register clock signal pulses;
means connected to the N-bit shift register for providing the N-bit message code to the N-bit shift register in one condition; and
means receiving the N-bit shift register output signal, having a portion generating a message bit complement for each message bit clocked from the N-bit shift register and providing the message bit followed by the message bit complement for each message bit of the (N) bit message code in a serial manner via an output signal, said last-mentioned output signal being the digital encoder output signal.
- means receiving the transmitter master clock signal and providing a shift register clock signal in response thereto, the shift register clock signal having a frequency coherently related to the transmitter master clock signal frequency;
-
33. The apparatus of claim 32 wherein the means generating the message bits and the message bit complements is defined further to include:
- gate means receiving the shift register clock signal and the N-bit shift register output signal providing an output signal having a logic level corresponding to the message bit logic level on the N-bit shift register output signal when receiving a shift register clock signal in the high state;
an inverter receiving the shift register clock signal and providing an output signal in the high state in response to a received shift register clock signal in the low state and providing an output signal in the low state in response to a received shift register clock signal in the high state;
an inverter receiving the N-bit shift register output signal and providing an output signal in the high state in response to a received N-bit shift register output signal in the low state and providing an output signal in the low state in response to a received N-bit shift register output signal in the high state;
gate means receiving the first-mentioned inverter output signal and receiving the second-mentioned inverter output signal and providing an output signal having a logic level corresponding to the complement of the message bit on the N-bit shift register output signal in a low state of the shift register clock signal; and
means receiving the first-mentioned gate means output signal and receiving the last-mentioned gate means output signal and providing the digital encoder output signal having a logic level corresponding to the message bit clocked from the N-bit shift register in the high state of the shift register clock signal and providing the digital encoder output signal having a logic level corresponding to the complement of the message bit clocked from the N-bit shift register in the low state of the shift register clock signal.
- gate means receiving the shift register clock signal and the N-bit shift register output signal providing an output signal having a logic level corresponding to the message bit logic level on the N-bit shift register output signal when receiving a shift register clock signal in the high state;
-
34. The apparatus of claim 33 wherein the means providing the transmitter shift register clock signal includes:
- a counter receiving the transmitter master clock signal and providing the shift register clock signal having a frequency of one-half the frequency of the received transmitter master clock signal, the message bit being provided during a half cycle of the shift register clock signal in the high state of the shift register clock signal and the complement of the preceding message bit being provided during the next half cycle of the shift register clock signal in the low state of the shift register clock signal.
-
35. The apparatus of claim 33 wherein the transmitter N-bit shift register output signal is connected to the input of the N-bit shift register, the message bit clocked from the N-bit shift register being clocked back into the N-bit shift register and the message bits of the N-bit message code being provided cyclically via the N-bit shift register output signal.
-
36. The apparatus of claim 35 wherein the means transmitting the FSK generator output signal has an operative and an inoperative condition, said means transmitting the FSK generator output signal in the operative condition thereof;
- and wherein the apparatus is defined further to include;
an M-counter connected to the digital encoder and the means transmitting the FSK generator output signal, the M-counter providing an output signal in the high state connected to the means transmitting the FSK generator output signal and rendering the means transmitting the FSK generator output signal inoperative in response to the N-bit message code being repeated a predetermined number (M) times, the M-counter output signal being returned to the low state in a predetermined period of time corresponding to the time required to repeat the N-bit message code the predetermined number (M) times.
- and wherein the apparatus is defined further to include;
-
37. The apparatus of claim 33 defined further to include:
- first counter means receiving the shift register clock signal and counting the number of message bits clocked from the N-bit shift register in an activated condition of the first counter means, the first counter means producing an output signal in the high state in response to the predetermined number (N) message bits being clocked from the N-bit shift register;
gate means receiving the transmitter master clock signal and the first counter means output signal, the gate means providing the transmitter master clock signal in the low state of the received first counter means output signal and inhibiting the transmitter master clock signal in the high state of the first counter means output signal; and
second counter means receiving the transmitter master clock signal and providing an output signal in the high state in response to a received predetermined number of transmitter
- first counter means receiving the shift register clock signal and counting the number of message bits clocked from the N-bit shift register in an activated condition of the first counter means, the first counter means producing an output signal in the high state in response to the predetermined number (N) message bits being clocked from the N-bit shift register;
-
38. A communication apparatus for communicating time division binary codes comprising a predetermined number of message bits, having logic levels representing logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros,'"'"''"'"''"'"''"'"' from a transmitter station to a receiver station, the apparatus comprising:
- means in the transmitter station having a predetermined message code comprising a predetermined number (N) message bits, generating a message bit complement for each message bit of the (N) bit message code and providing each message bit followed by the message bit complement of the preceding message bit in a serial manner via an output signal;
means in the transmitter station generating a synchronization signal prior to the generation of the (N) message bits and the (N) message bit complements;
means receiving the output signal from the means providing the message bits and the message bit complements, receiving the synchronization signal, transmitting the synchronization signal and then transmitting each of the message bits of the (N) bit message code followed by the message bit complements in a serial manner;
means in the receiver station receiving the transmitted signal and providing an output signal in response to a received synchronization signal;
an N-counter receiving and being activated by the output signal provided in response to the received synchronization signal to count input pulses connected thereto And to provide an output signal in response to a received predetermined number (N) input pulses;
means in the receiver station receiving the transmitted signal and providing an output signal in response to each received message bit followed by the message bit complement, the output signal being connected to the N-counter and providing the input pulses for incrementing the N-counter;
means in the receiver station receiving the transmitted signal and providing a reset signal in response to a received message bit followed by a signal other than the message bit complement, the reset signal being connected to the N-counter and resetting the N-counter; and
an M-counter in the receiver station receiving the N-counter output signal and providing a valid data signal in response to a predetermined number (M) received N-counter output signals, the valid data signal indicating the reception of each message bit followed by the message bit complement of each message bit of the (N) bit message code the predetermined number (M) times.
- means in the transmitter station having a predetermined message code comprising a predetermined number (N) message bits, generating a message bit complement for each message bit of the (N) bit message code and providing each message bit followed by the message bit complement of the preceding message bit in a serial manner via an output signal;
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39. A frequency shift key (FSK) method for communicating time division binary message codes comprising a predetermined number (N) of message bits, having logic levels representing locigal '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros,'"'"''"'"''"'"''"'"' from a transmitter station to a receiver station, the method comprising the steps of:
- generating an FSK signal having a predetermined frequency;
receiving the FSK signal and producing a transmitter master clock signal having a frequency coherently related to the received FSK signal frequency;
receiving the transmitter master clock signal and producing the message bits of the N-bit message code in a serial manner in response to the received transmitter master clock signal and at a rate coherently related to the received FSK signal frequency;
receiving the message bits produced in response to the transmitter master clock signal and controlling the frequency of the generated FSK signal to provide an FSK signal having a frequency (fs) for each received message bit of a logic level representing a logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"' and a frequency (fm) for each received message bit of a logic level representing a logical '"'"''"'"''"'"''"'"'one,'"'"''"'"''"'"''"'"' the FSK signal having a predetermined transmission time for an (N) bit message code independent of the number of logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros'"'"''"'"''"'"''"'"' comprising the (N) bit message code;
transmitting the FSK signal;
receiving the transmitted FSK signal and producing a receiver master clock signal having a frequency coherently related to the received, transmitted FSK signal frequency; and
receiving the receiver master clock signal and the transmitted FSK signal and decoding the transmitted FSK signal to derive the message code at a rate determined via the receiver master clock signal coherently related to the FSK signal frequency.
- generating an FSK signal having a predetermined frequency;
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40. A method for transmitting a time division binary message code comprising a predetermined number (N) of message bits, having logic levels representing logical '"'"''"'"''"'"''"'"'ones'"'"''"'"''"'"''"'"' and logical '"'"''"'"''"'"''"'"'zeros,'"'"''"'"''"'"''"'"' the method comprising the steps of:
- transmitting each message bit of the (N) bit message code, including the steps of;
producing each message bit of the N-bit message code in a serial manner;
generating an FSK signal having a frequency (fs) for each produced message bit having a logic level representing a logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"'; and
generating an FSK signal having a frequency (fm) for each produced message bit having a logic level representing a logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"'; and
transmitting a message bit complement following the transmission of the message bit for each message bit of the (N) bit message code, including the steps of;
producing the message bit complement of each message bit of the N-bit message code, each message bit complement being produced immediately following the produced message bit;
generating an FSK signal having a frequency (fs) for each produced message bit complement having a logic level representing a logical '"'"''"'"''"'"''"'"'one'"'"''"'"''"'"''"'"'; and
generating an FSK signal having a frequency (fm) for each produced message bit complement having a logic level representing a logical '"'"''"'"''"'"''"'"'zero'"'"''"'"''"'"''"'"', the transmission time for the N-bit message code being
- transmitting each message bit of the (N) bit message code, including the steps of;
-
41. The method of claim 40 defined further to include:
- receiving each generated FSK signal and producing a transmitter master clock signal derived from the received FSK signals and having a frequency coherently related to the received FSK signal frequency; and
receiving the transmitter master clock signal and producing each message bit and each message bit complement in response to the received transmitter master clock signal at a frequency coherently related to the FSK signals.
- receiving each generated FSK signal and producing a transmitter master clock signal derived from the received FSK signals and having a frequency coherently related to the received FSK signal frequency; and
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42. A method for communicating time division binary codes comprising a predetermined number (N) of message bits from a transmitter station to a receiver station, the method comprising the steps of:
- transmitting each message bit of the (N) bit message code;
transmitting a message bit complement following the transmission of the message bit for each message bit of the (N) bit message code;
transmitting a synchronization signal prior to the transmission of the (N) message bits and the (N) message bit complements;
receiving the synchronization signal, the message bits and the message bit complements;
providing a reset signal in response to receiving a message bit followed by a signal other than the message bit complement;
counting the number of message bits followed by the message bit complements received after receiving the synchronization signal and providing an output signal in response to receiving (N) message bits followed by the message bit complements indicating the reception of the N-bit message code;
receiving the reset signal and resetting the counting of the number of message bits followed by the message bit complements in response to receiving the reset signal; and
receiving the output signals indicating the reception of the N-bit message code and providing a valid data signal in response to receiving a predetermined number of output signals indicating the reception of the N-bit message code the predetermined number of times.
- transmitting each message bit of the (N) bit message code;
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43. The method of claim 42 wherein the step of transmitting the synchronization signal is defined further to include:
- producing a synchronization signal having a logic level corresponding to the logic level of the first message bit of the N-bit message code and a time duration corresponding to the duration of two first message bits.
Specification