Digital multiplexer system

• US 3,931,473 A
• Filed: 09/03/1974
• Issued: 01/06/1976
• Est. Priority Date: 09/03/1974
• Status: Expired due to Term

• Current Assignee: CSE Technologies Incorporated
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Ferris, Walton C. Jr.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US05/502,293
• Time in Patent Office: 490 Days
• Field of Search: 179/15 AF, 179/15 BS, 179/15 A
• US Class Current: 370/541
• CPC Class Codes: H04J 3/0602 Systems characterised by the synchronising information used
• CPC Class Codes: H04J 3/07 using pulse stuffing for systems with different or fluctuating information rates or bit rates

Abstract

A second level multiplexer for a PCM data system provides for fast reframing by utilizing the stuff words in the frame organization in addition to the main framing word. This provides a clear indication of a misframe condition. In addition, integration of errors by a counter supplies immunity to medium amounts of noise. The foregoing provides for an optimum environment for frame synchronized scrambling and descrambling to be accomplished.

Claims

1. A digital multiplexer system for multiplexing a plurality of digital data channels into a serial bit stream, which is divided into frames by a frame counter means, each frame being indicated by a frame pattern for transmission to a demultiplexing receiver which also includes a frame counter means such system using a plurality of stuff words having redundant bits in said bit stream to indicate whether or not to substitute at least one stuff bit to accommodate timing irregularities, said system comprising;

means for sensing said stuff words and for providing an error signal if said bits of said stuff words are not redundant because of an error during said transmission, means for sensing said frame pattern, counting means for counting said errors and providing a misframe signal, coincidence means responsive to said means for sensing said frame pattern for sensing a misframe signal for resetting said frame counter means of said receiver.

2. A system as in claim 1 which includes pseudo-random word generators in the transmission and receiver portions of the system for respectively scrambling and descrambling said serial bit stream the word generator in said receiver portion being reset by said coincidence means.

3. A system as in claim 1 where said counting means provides said misframe signal after a predetermined plurality of errors have been counted.

4. A system as in claim 3 where said counting means are initially reset to provide a misframe signal after only relatively few errors are received.