Multilayer printed circuit board

• US 3,934,335 A
• Filed: 10/16/1974
• Issued: 01/27/1976
• Est. Priority Date: 10/16/1974
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nelson, Mark A.
• Primary Examiner(s): Lanham, C. W.
• Assistant Examiner(s): Walkowski, Joseph A.
• Application Number:
  US05/515,282
• Time in Patent Office: 468 Days
• Field of Search: 29/625, 96/36.2, 96/38.4, 174/68.5, 117/212, 117/213, 117/215, 117/217, 117/5.5, 117/6, 117/8.5, 117/66, 117/67, 317/101 A, 317/101 B
• US Class Current: 29/847
• CPC Class Codes: H05K 1/05 Insulated conductive substrates, e.g. insulated metal substrate
• CPC Class Codes: H05K 2201/09563 Metal filled via
• CPC Class Codes: H05K 2201/09581 Applying an insulating coating on the walls of holes
• CPC Class Codes: H05K 2201/09809 Coaxial layout
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/0094 Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
• CPC Class Codes: H05K 3/184 using masks
• CPC Class Codes: H05K 3/185 by making a catalytic pattern by photo-imaging
• CPC Class Codes: H05K 3/282 for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: H05K 3/426 initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core
• CPC Class Codes: H05K 3/4608 comprising an electrically conductive base or core
• CPC Class Codes: Y10T 29/49156 with selective destruction of conductive paths

Abstract

Multilayer printed circuit board is fabricated by coating a suitable substrate, metal, plastic, paper, with a photosensitive coating, exposing the photosensitive coating to form a dielectric thereof, coating the dielectric layer with a coating of a photosensitive chemical solution, selectively imaging and developing the photosensitive coating to form a desired circuit pattern on the dielectric coating, forming a first layer of circuitry by coating the circuit pattern with a conducting material, coating the circuitry bearing layer with a second layer of photosensitive material, selectively exposing and developing the second layer of photosensitive material to form a dielectric with open windows to the first circuit layer, coating the second dielectric layer of the first circuitry with a coating of photosensitive chemical solution, selectively imaging and developing the coating of photosensitive chemical solution to form a circuit pattern and an interconnect pattern and forming a conductor layer of circuitry and interconnects, the interconnect metallization connecting the second circuitry layer with the first circuitry layer, repeating the process to form additional circuitry layers to perform a desired electrical function and forming on the last dielectric layer a metallization such as either a solder mask for circuit terminals or a ground plane and thereafter either retaining the substrate if desired for, for example, a heat sink or additional support or both, or removing the substrate to form a very light weight multilayer printed circuit board.

Claims

1. A method for fabricating a multilayer printed wiring circuit board comprising:

a. forming a dielectric layer on a substrate;

b. coating the dielectric layer with a first layer of photosensitive material;

c. selectively exposing the first layer of photosensitive material to form a layer defining a first conductor pattern of exposed photosensitive material;

d. forming the conductor pattern with a conductor material to form conductors in the conductor pattern;

e. coating the circuit bearing layer with a layer of photosensitive substrate material;

f. selectively exposing the layer of photosensitive substrate material to form a second dielectric layer defining circuit layer interconnections;

g. coating the second dielectric layer with a second layer of photosensitive material;

h. selectively exposing the second layer of photosensitive material to form a layer defining a second circuit pattern of exposed photosensitive material;

i. forming the second conductor pattern with electrically conducting material; and

j. repeating steps e through i to form a plurality of electrically

2. A method according to claim 1 further comprising forming apertures of a feed through hole pattern in the substrate prior to forming the dielectric layer on the substrate and coating the holes of the hole pattern with a

3. A method according to claim 1 wherein the coatings of photosensitive

4. A method according to claim 1 wherein the coatings of photosensitive

5. A method according to claim 1 further comprising removing the core

6. A method according to claim 2 comprising forming the multilayer circuits

7. A method according to claim 1 further comprising forming a ground plane

8. A method according to claim 1 further comprising forming a metallization

9. A method according to claim 8 wherein the desired metallization pattern

10. A method according to claim 1 further comprising forming a solder mask

11. A method according to claim 10 wherein the soldering mask comprises selectively coating the outer circuit layer with an epoxy to define areas to be soldered, curing the epoxy layer;

and coating the epoxy layer with a protective coating to prevent oxidation of the solder areas.