Control arrangement for an electrostatographic reproduction apparatus

• US 3,936,182 A
• Filed: 08/12/1974
• Issued: 02/03/1976
• Est. Priority Date: 08/12/1974
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Sheikh, Sikander
• Primary Examiner(s): Moses, Richard L.
• Application Number:
  US05/496,666
• Time in Patent Office: 540 Days
• Field of Search: 355/14, 355/4, 355/103, 355/108-111
• US Class Current: 399/77
• CPC Class Codes: G03G 21/14 Electronic sequencing control

Abstract

A copier apparatus control means is disclosed which comprises a digital processor adapted for storing and executing a stored control program. The logical organization of the digital processor is simplified by employing non-destructive memory program storage means. Control of the apparatus is programmable by altering the program through substitution of the non-destructive memory means.

Claims

1. An electrostatographic copying apparatus comprising:

means for forming a latent electrostatic image, for developing the image and for transferring the image to a record medium;

said means including a plurality of operating members adapted for actuation at predetermined times during a copy reduction cycle; and

a plurality of members for providing electrical representations of machine conditions or selected modes of operation during a copying cycle;

apparatus control means coupled to said operative and machine condition members for sensing said electrical representations and for causing a predetermined actuation of said operative members in accordance with the representation of said condition member;

said control means having a digital processor adapted for storing and executing a stored apparatus control program, said processor including a non-destructive memory means for storing an apparatus control program and which is adapted for altering the program by replacement with a substitute memory means.

2. The copier apparatus of claim 1 including a second memory means for sequentially controlling the execution of the program of instructions stored in said non-destructive memory.

3. The copier apparatus of claim 2 wherein said second memory means comprises a non-destructive memory for storing a program which controls the sequence of the execution program in said first non-destructive memory and which is adapted for modification to the sequence program by replacement with a substitute non-destructive memory means.

4. The apparatus of claim 2 wherein said first non-destructive memory means stores a program of instruction words, each of said instruction words includes a field of bits defining an operation code, said code defining an operational step for the control means, a decoding means including a memory having a plurality of control instructions stored at memory locations in said decoding memory, and means for coupling said operation code field of bits from said first memory to said decoding memory for addressing and selecting one of said decoding memory instructions.

5. The copier apparatus of claim 4 wherein said decoding memory means comprises a non-destructive memory and which is adapted for modifying the processor control instructions by replacement with a substitute memory means.

6. A copier apparatus comprising:

a plurality of operative members adapted for actuation at predetermined times during a copy reproduction cycle,

each of said members comprising electrically energizable means coupled in a matrix array;

a plurality of members representative of the condition of the copier during a reproduction cycle,

each of said condition representing members adapted for providing an electrical signal and coupled in a matrix array;

an apparatus control means coupled to said output and input matrices for causing a predetermined actuation of the operative members in accordance with the state of said condition representing members;

said control means having a digital processor adapted for executing a stored apparatus control program for controlling said apparatus;

an input buffer comprising a plurality of memory elements;

an output buffer comprising a plurality of memory elements;

means for simultaneously scanning said input matrix and said input buffer memory locations for transferring data from said input matrix to input buffer memory locations;

means for introducing control information from said apparatus control to said output buffer memory locations for energizing selective ones of said plurality of operative members;

said apparatus control including a plurality of memory and register members between which information is transferred at a relatively high rate and in an asynchronous manner with respect to said input and output buffers.

7. The apparatus of claim 6 wherein said control apparatus is adapted for entering data from said input matrix into said input buffer memory elements and for simultaneously entering data into said output buffer memory elements for actuating said operative members.

8. The apparatus of claim 7 wherein said processor includes a first non-destructive read-only memory for storing an execution program for the apparatus;

a second non-destructive read-only memory for controlling the execution of the sequence of program instructions stored in said first read-only memory;

means for sequentially addressing a plurality of memory locations in said second read-only memory and for simultaneously addressing a plurality of memory locations in said input buffer and output buffer memories;

a third instruction decoding read-only memory having a plurality of memory locations and storing processor control instructions for controlling the operation of said processor;

input bus means for receiving a plurality of inputs and selectively coupling one of said inputs to an output terminal of said bus means;

means for coupling the output of said bus and an operation control field of bits in an instruction word from said first read-only memory to said instruction decode memory and the output of said input bus to said instruction decode memory for addressing a memory location in said instruction decode memory;

means for applying input data to said bus control means from a plurality of data sources, said sources including copier apparatus condition registers, an auxiliary memory, and said input and output buffers; and

,

means for coupling a bus control field of bits in said instruction word from said first read-only memory to said bus control for selectively coupling one of said inputs to the output terminal of said bus control.

9. The processor of claim 8 including a second auxiliary memory, means for coupling said first non-destructive memory to said second auxiliary memory for addressing said second auxiliary memory at a memory location for the introduction of data thereto, and means for coupling said address-test field to said second auxiliary memory at an addressed location.

10. The processor of claim 8 including a timing counter means, means for coupling residue pulses to said timing counter for stepping said counter, a comparator means, means for applying the count in said counter means and the address-test field of an addressed memory location of said first non-destructive memory means to said comparator for providing an electrical output indication of the correspondence of said inputs for use by said processor.