Digital demodulator for phase-modulated waveforms

• US 3,938,052 A
• Filed: 05/09/1974
• Issued: 02/10/1976
• Est. Priority Date: 05/09/1974
• Status: Expired due to Term

• Current Assignee: AT&T Teletype Corporation (AT&T, Inc.)
• Original Assignee: Teletype Corp. (AT&T, Inc.)
• Inventors: Glasson, Jerry M., King, Ira S.
• Primary Examiner(s): Brody, Alfred L.
• Application Number:
  US05/468,325
• Time in Patent Office: 642 Days
• Field of Search: 329/104, 328/63, 328/109, 328/110, 328/117, 325/320, 178/88
• US Class Current: 329/310
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

Digital logic apparatus for demodulating a received phase-modulated carrier wave wherein phase-shifts between successive signalling intervals encode data elements. A shift register serially stores periodic samples of a squared version of the received wave. Exclusive-OR gates compare pairs of stored wave samples, each pair comprising a sample from a previous signalling interval and a sample from a current signalling interval. At least one of the exclusive-OR gates derives synchronizing signals for a local timing generator. For each data element, an integrator is associated with one of the exclusive-OR gates to accumulate a count related to the time during which pairs of similar samples are sensed by its exclusive-OR gate during each signalling interval. The integrator registering the highest count at the end of a given data interval signifies the data element received during that interval. An alternate embodiment is disclosed for less critical applications wherein outputs from digital filters indicate the received data elements.

Claims

1. A demodulator for a received wave having phase shifts between successive signalling intervals the phase shifts encoding data elements, which includes:

a timing generator, means for synchronizing the timing generator with the received wave, means for generating a squared version of the received wave, a shift register for storing periodic samples of the squared wave for a period encompassing a current signalling interval and at least a portion of a previous signalling interval, a plurality of exclusive-OR gates connected to stages of the shift register for comparing selected pairs of samples from the shift register; and

means controlled by the exclusive-OR gates and the timing generator for identifying which data element is received during each signalling interval, wherein the identifying means comprises;

a. for each data element;

i. a counter,

ii. an output gate connected to the counter for sensing when the counter reaches a particular count,

iii. means controlled by the timing generator and the exclusive-OR gate whose selected output state is associated with the data element for incrementing the counter at a first periodic rate during a mid-portion of each signalling interval when the output signal of the exclusive-OR gate is in the selected state;

b. means controlled by the timing generator and the output gates for simultaneously incrementing all of the counters at a second periodic rate higher than the first periodic rate during a portion of each signalling interval subsequent to the mid-portion until one of the output gates becomes enabled, thus identifying the data element associated with the enabled output gate as received during the signalling interval; and

c. means controlled by the timing generator for resetting the counters subsequent to one of the output gates becoming enabled and before the mid-portion of the next signalling interval.

2. Apparatus of claim 1 wherein the incrementing means for each data element further comprises:

means controlled by the timing generator for incrementing the counter at different periodic rates during different periods of the mid-portion of each signalling interval to thereby give different emphasis to the received wave during the different periods of the mid-portion.

3. Apparatus for demodulating a received wave having phase-shifts of +45°

, +1350°

, +_"° and

+315°

between successive signalling intervals, the phase shifts encoding four dibit combinations, which comprises;

a timing generator;

means for synchronizing the timing generator with the received wave;

means for generating a squared version of the received wave;

a shift register having a plurality of stages for serially storing samples at a first periodic rate of the squared wave encompassing a current signalling interval and at least a portion of a previous signalling interval;

a first exclusive-OR gate associated with the first and the second of the dibit combinations for comparing samples stored in two stages selected to encompass the span between like-phased samples of the waves from the previous and current signalling intervals;

a first counter associated with the first dibit combination;

a second counter associated with the second dibit combination;

means controlled by the timing generator and the first exclusive-OR gate for incrementing at the first periodic rate during a mid-portion of each signalling interval, the first counter when the output of the first exclusive-OR gate indicates that the samples compared thereby agree, and the second counter when the output of the first exclusive-OR gate indicates that the samples compared thereby differ;

a second exclusive-OR gate associated with the third and the fourth of the dibit combinations for comparing samples stored in two stages selected to encompass the span between like-phased samples of the waves from the previous and current signalling intervals;

a third counter associated with the third dibit combination;

a fourth counter associated with the fourth dibit combination;

means controlled by the timing generator and the second exclusive-OR gate for periodically incrementing at the first periodic rate, during a mid-portion of each signalling interval, the third counter when the output of the second exclusive-OR gate indicates that the samples compared thereby agree, and the fourth counter when the output of the second exclusive-OR gate indicates that the samples compared thereby differ;

four output gates, one of the output gates being connected to each counter for sensing when that counter reaches a particular count;

means controlled by the timing generator and the output gates for simultaneously incrementing the counters at a second periodic rate higher than the first periodic rate during a portion of each signalling interval subsequent to the mid-portion until one of the output gates becomes enabled, thus identifying the data element associated with the enabled output gate as received during the signalling interval; and

means controlled by the timing generator for resetting the counters subsequent to one of the output gates becoming enabled and before the mid-portion of the next signalling interval.

4. Apparatus of claim 3 wherein the received wave comprises an 1800 Hz carrier wave, the signalling intervals are repeated at a rate of 1200 per second, the first periodic rate is substantially 96 operations per signalling interval, the shift register comprises 112 stages numbered 1 to 112, samples being shifted in the direction from stage 1 to stage 112, the first exclusive-OR gate compares samples from stages 8 and 96, and the second exclusive-OR gate compares samples from stages 8 and 112.

5. Apparatus of claim 4 wherein the means for incrementing the first and second counters further comprises:

means controlled by the timing generator for incrementing the first and second counters, according to the output of the first exclusive-OR gate, at a periodic rate of 192 counts per signalling interval during substantially the middle third of each signalling interval, and at the first periodic rate during substantially the second sixth and the fifth sixth of each signalling interval, and wherein the means for incrementing the third and fourth counters further comprises;

means controlled by the timing generator for incrementing the third and fourth counters, according to the output of the second exclusive-OR gate, at the periodic rate of 192 counts per signalling interval during substantially the middle third of each signalling interval, and at the first periodic rate during substantially the second sixth and the fifth sixth of each signalling interval.

6. A demodulator for a received wave having phase shifts of +45°

, +135°

, +225° and

+315°

between successive signalling intervals that encode a respective plurality of dibit combinations of the type having;

a timing generator, means for synchronizing the timing generator with the received wave, means for generating a squared version of the received wave, a shift register for storing periodic samples of the squared wave for a period encompassing a current signalling interval and at least a portion of a previous signalling interval, means responsive to selected samples from the shift register and controlled by the timing generator for decoding data elements received during each signalling interval and for loading the received data elements into an output register, characterized in that;

the means for decoding data elements comprises a pair of exclusive-OR gates connected to selected stages of the shift register for comparing pairs of samples from the shift register;

a first filter connected to the output of the first one of the exclusive-OR gates to eliminate shortterm transitions in the output signal thereof, the first exclusive-OR gate being connected to compare the first sample with the second sample delayed by one signalling interval with respect to the first sample;

a second filter connected to the output of the second one of the exclusive-OR gates to eliminate short-term transitions in the output signal thereof, the second exclusive-OR gate being connected to compare the first sample with the third sample removed drom the second sample by an interval occupied by a 90°

segment of the received wave, the short-term transitions eliminated by the first and second filters having a duration shorter than the interval occupied by a 90°

segment of the received wave; and

means controlled by the timing generator for loading the output of the first filter directly into one stage of the output register to represent one bit of the received dibit combination and for loading the output of the second filter directly into another stage of the output register to represent the other bit of the received dibit combination.

7. A demodulator of claim 6 wherein the means for synchronizing the timing generator with the received wave is directly connected to and responsive to the outputs of the first and second filters.