Process for fabricating dielectrically isolated semiconductor components of an integrated circuit

• US 3,938,176 A
• Filed: 09/24/1973
• Issued: 02/10/1976
• Est. Priority Date: 09/24/1973
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sloan, Benjamin Johnston Jr.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US05/400,492
• Time in Patent Office: 869 Days
• Field of Search: 317/235 F, 357/40, 357/45, 357/48, 357/49
• US Class Current: 257/526
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76297 Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/02 Contacts, special
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

Disclosed is a method of fabricating dielectrically isolated semiconductor components of an integrated circuit, and the semiconductor component formed by this method, each component having a plurality of high conductivity regions extending from the interior of said component to the surface thereof to provide high conductivity paths to selected semiconductor regions of the component.

Claims

1. A dielectrically isolated semiconductor component of an integrated circuit in a substrate, comprising:

a. a dielectrically isolated pocket of monocrystalline semiconductor material of one conductivity type in said substrate, said isolation being furnished by a layer of insulating material between said pocket and the remainder of said substrate, said insulating layer having selected spaced ridges in close proximity to one surface of said pocket;

b. a region of said one conductivity type but of greater conductivity in said pocket and adjacent said insulating layer;

c. a plurality of rows of semiconductor regions of the opposite conductivity type in said pocket; and

, d. a plurality of rows of high conductivity regions of said one conductivity type in said pocket, alternating with said rows of semiconductor regions, said high conductivity regions extending from the surface of said pocket in contact with said region of high conductivity, along said ridges.

2. A semiconductor component as described in claim 1, wherein said pocket is silicon.

3. The semiconductor component as described in claim 1, wherein said insulating layer is silicon oxide.

4. The semiconductor component as described in claim 1, wherein said insulating layer is silicon nitride.

5. The semiconductor component as described in claim 1, wherein said material is polycrystalline silicon.

6. An integrated circuit of dielectrically isolated semiconductor components in a substrate, comprising:

a. dielectrically isolated pockets of monocrystalline semiconductor material of one conductivity type in said substrate, said isolation being furnished by a layer of insulating material between said pockets and the remainder of said substrate, said insulating layer having selected spaced ridges in close proximity to one surface of each of said pockets;

b. a region of said one conductivity type but of higher conductivity in each of said pockets and adjacent said insulating layer;

c. a plurality of rows of semiconductor regions of the opposite conductivity type in each of said pockets; and

,

d. a plurality of rows of high conductivity regions of said one conductivity type in each of said pockets, alternating with said rows of semiconductor regions, said high conductivity regions extending from the surface of said pockets in contact with said region of high conductivity in each of said pockets, along said ridges.